297 lines
9.3 KiB
C
297 lines
9.3 KiB
C
/*
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* libqos AHCI functions
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*
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* Copyright (c) 2014 John Snow <jsnow@redhat.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <glib.h>
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#include "libqtest.h"
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#include "libqos/ahci.h"
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#include "libqos/pci-pc.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/pci_regs.h"
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/**
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* Allocate space in the guest using information in the AHCIQState object.
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*/
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uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes)
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{
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g_assert(ahci);
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g_assert(ahci->parent);
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return qmalloc(ahci->parent, bytes);
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}
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void ahci_free(AHCIQState *ahci, uint64_t addr)
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{
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g_assert(ahci);
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g_assert(ahci->parent);
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qfree(ahci->parent, addr);
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}
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/**
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* Locate, verify, and return a handle to the AHCI device.
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*/
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QPCIDevice *get_ahci_device(uint32_t *fingerprint)
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{
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QPCIDevice *ahci;
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uint32_t ahci_fingerprint;
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QPCIBus *pcibus;
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pcibus = qpci_init_pc();
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/* Find the AHCI PCI device and verify it's the right one. */
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ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
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g_assert(ahci != NULL);
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ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
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switch (ahci_fingerprint) {
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case AHCI_INTEL_ICH9:
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break;
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default:
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/* Unknown device. */
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g_assert_not_reached();
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}
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if (fingerprint) {
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*fingerprint = ahci_fingerprint;
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}
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return ahci;
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}
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void free_ahci_device(QPCIDevice *dev)
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{
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QPCIBus *pcibus = dev ? dev->bus : NULL;
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/* libqos doesn't have a function for this, so free it manually */
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g_free(dev);
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qpci_free_pc(pcibus);
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}
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/*** Logical Device Initialization ***/
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/**
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* Start the PCI device and sanity-check default operation.
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*/
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void ahci_pci_enable(AHCIQState *ahci)
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{
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uint8_t reg;
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start_ahci_device(ahci);
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switch (ahci->fingerprint) {
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case AHCI_INTEL_ICH9:
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/* ICH9 has a register at PCI 0x92 that
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* acts as a master port enabler mask. */
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reg = qpci_config_readb(ahci->dev, 0x92);
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reg |= 0x3F;
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qpci_config_writeb(ahci->dev, 0x92, reg);
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/* 0...0111111b -- bit significant, ports 0-5 enabled. */
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ASSERT_BIT_SET(qpci_config_readb(ahci->dev, 0x92), 0x3F);
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break;
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}
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}
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/**
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* Map BAR5/ABAR, and engage the PCI device.
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*/
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void start_ahci_device(AHCIQState *ahci)
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{
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/* Map AHCI's ABAR (BAR5) */
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ahci->hba_base = qpci_iomap(ahci->dev, 5, &ahci->barsize);
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g_assert(ahci->hba_base);
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/* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
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qpci_device_enable(ahci->dev);
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}
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/**
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* Test and initialize the AHCI's HBA memory areas.
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* Initialize and start any ports with devices attached.
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* Bring the HBA into the idle state.
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*/
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void ahci_hba_enable(AHCIQState *ahci)
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{
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/* Bits of interest in this section:
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* GHC.AE Global Host Control / AHCI Enable
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* PxCMD.ST Port Command: Start
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* PxCMD.SUD "Spin Up Device"
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* PxCMD.POD "Power On Device"
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* PxCMD.FRE "FIS Receive Enable"
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* PxCMD.FR "FIS Receive Running"
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* PxCMD.CR "Command List Running"
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*/
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uint32_t reg, ports_impl;
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uint16_t i;
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uint8_t num_cmd_slots;
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g_assert(ahci != NULL);
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/* Set GHC.AE to 1 */
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ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
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reg = ahci_rreg(ahci, AHCI_GHC);
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ASSERT_BIT_SET(reg, AHCI_GHC_AE);
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/* Cache CAP and CAP2. */
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ahci->cap = ahci_rreg(ahci, AHCI_CAP);
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ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
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/* Read CAP.NCS, how many command slots do we have? */
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num_cmd_slots = ((ahci->cap & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
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g_test_message("Number of Command Slots: %u", num_cmd_slots);
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/* Determine which ports are implemented. */
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ports_impl = ahci_rreg(ahci, AHCI_PI);
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for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
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if (!(ports_impl & 0x01)) {
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continue;
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}
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g_test_message("Initializing port %u", i);
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reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
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if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
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AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
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g_test_message("port is idle");
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} else {
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g_test_message("port needs to be idled");
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ahci_px_clr(ahci, i, AHCI_PX_CMD,
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(AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
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/* The port has 500ms to disengage. */
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usleep(500000);
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reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
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g_test_message("port is now idle");
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/* The spec does allow for possibly needing a PORT RESET
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* or HBA reset if we fail to idle the port. */
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}
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/* Allocate Memory for the Command List Buffer & FIS Buffer */
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/* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
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ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);
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qmemset(ahci->port[i].clb, 0x00, 0x100);
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g_test_message("CLB: 0x%08" PRIx64, ahci->port[i].clb);
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ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);
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g_assert_cmphex(ahci->port[i].clb, ==,
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ahci_px_rreg(ahci, i, AHCI_PX_CLB));
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/* PxFB space ... 0x100, as in 4.2.1 p 35 */
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ahci->port[i].fb = ahci_alloc(ahci, 0x100);
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qmemset(ahci->port[i].fb, 0x00, 0x100);
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g_test_message("FB: 0x%08" PRIx64, ahci->port[i].fb);
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ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);
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g_assert_cmphex(ahci->port[i].fb, ==,
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ahci_px_rreg(ahci, i, AHCI_PX_FB));
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/* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
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ahci_px_wreg(ahci, i, AHCI_PX_SERR, 0xFFFFFFFF);
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ahci_px_wreg(ahci, i, AHCI_PX_IS, 0xFFFFFFFF);
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ahci_wreg(ahci, AHCI_IS, (1 << i));
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/* Verify Interrupts Cleared */
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reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
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g_assert_cmphex(reg, ==, 0);
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reg = ahci_px_rreg(ahci, i, AHCI_PX_IS);
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g_assert_cmphex(reg, ==, 0);
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reg = ahci_rreg(ahci, AHCI_IS);
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ASSERT_BIT_CLEAR(reg, (1 << i));
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/* Enable All Interrupts: */
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ahci_px_wreg(ahci, i, AHCI_PX_IE, 0xFFFFFFFF);
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reg = ahci_px_rreg(ahci, i, AHCI_PX_IE);
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g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
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/* Enable the FIS Receive Engine. */
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ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
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reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
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ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
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/* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
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* physical presence, a device is present and may be started. However,
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* PxSERR.DIAG.X /may/ need to be cleared a priori. */
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reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR);
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if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
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ahci_px_set(ahci, i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
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}
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reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD);
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if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
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reg = ahci_px_rreg(ahci, i, AHCI_PX_SSTS);
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if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
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/* Device Found: set PxCMD.ST := 1 */
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ahci_px_set(ahci, i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
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ASSERT_BIT_SET(ahci_px_rreg(ahci, i, AHCI_PX_CMD),
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AHCI_PX_CMD_CR);
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g_test_message("Started Device %u", i);
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} else if ((reg & AHCI_PX_SSTS_DET)) {
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/* Device present, but in some unknown state. */
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g_assert_not_reached();
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}
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}
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}
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/* Enable GHC.IE */
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ahci_set(ahci, AHCI_GHC, AHCI_GHC_IE);
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reg = ahci_rreg(ahci, AHCI_GHC);
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ASSERT_BIT_SET(reg, AHCI_GHC_IE);
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/* TODO: The device should now be idling and waiting for commands.
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* In the future, a small test-case to inspect the Register D2H FIS
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* and clear the initial interrupts might be good. */
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}
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/**
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* Pick the first implemented and running port
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*/
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unsigned ahci_port_select(AHCIQState *ahci)
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{
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uint32_t ports, reg;
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unsigned i;
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ports = ahci_rreg(ahci, AHCI_PI);
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for (i = 0; i < 32; ports >>= 1, ++i) {
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if (ports == 0) {
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i = 32;
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}
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if (!(ports & 0x01)) {
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continue;
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}
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reg = ahci_px_rreg(ahci, i, AHCI_PX_CMD);
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if (BITSET(reg, AHCI_PX_CMD_ST)) {
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break;
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}
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}
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g_assert(i < 32);
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return i;
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}
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