Richard Henderson ca5bed07d0 tcg/ppc: Use new registers for LQ destination ... LQ has a constraint that RTp != RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-stable@nongnu.org Fixes: 526cd4ec01 ("tcg/ppc: Support 128-bit load/store") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-01-11 08:47:45 +11:00
..
aarch64
arm
i386	tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates	2024-01-11 08:46:35 +11:00
loongarch64	tcg/loongarch64: Fix tcg_out_mov() Aborted	2023-11-21 10:32:42 +08:00
mips
ppc	tcg/ppc: Use new registers for LQ destination	2024-01-11 08:47:45 +11:00
riscv
s390x
sparc64
tci
meson.build	meson: remove config_targetos	2023-12-31 09:11:28 +01:00
optimize.c
region.c
tcg-common.c
tcg-internal.h
tcg-ldst.c.inc
tcg-op-gvec.c
tcg-op-ldst.c	tcg: Reduce serial context atomicity earlier	2023-12-12 13:35:19 -08:00
tcg-op-vec.c
tcg-op.c
tcg-pool.c.inc
tcg.c	tcg/ppc: Use new registers for LQ destination	2024-01-11 08:47:45 +11:00
tci.c