Max Filippov e848dd4248 target-xtensa: add basic checks to icache opcodes ... Check privilege level for privileged instructions (IHU, III, IIU and IPFL are privileged), memory accessibility for instructions that reference memory (IH* and IPFL) and windowed register validity for all instruction cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2014-02-24 04:47:01 +04:00
..
core-dc232b
core-dc233c
core-fsf
core-dc232b.c
core-dc233c.c	target-xtensa: add missing DEBUG section to dc233c config	2013-11-08 09:26:07 +04:00
core-fsf.c
cpu-qom.h	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
cpu.c	cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"	2013-07-29 15:29:15 +02:00
cpu.h	target-xtensa: avoid double-stopping at breakpoints	2013-07-29 18:35:45 +04:00
gdbstub.c	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
helper.c	exec: Make ldl_*_phys input an AddressSpace	2014-02-11 22:56:54 +10:00
helper.h	target-xtensa: add basic checks to icache opcodes	2014-02-24 04:47:01 +04:00
Makefile.objs	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
op_helper.c	target-xtensa: add basic checks to icache opcodes	2014-02-24 04:47:01 +04:00
overlay_tool.h
translate.c	target-xtensa: add basic checks to icache opcodes	2014-02-24 04:47:01 +04:00
xtensa-semi.c	exec: Change cpu_memory_rw_debug() argument to CPUState	2013-07-23 02:41:33 +02:00