e8e4994313
The Cadence GEM hardware allows incoming data to be 'screened' based on some register values. Add support for these screens. We also need to increase the max regs to avoid compilation failures. These new registers are implemented in the next patch. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 73e69a8ad9fa2763e9f68f71eaf2469dd5744fcc.1469727764.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/*
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* QEMU Cadence GEM emulation
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*
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* Copyright (c) 2011 Xilinx, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef CADENCE_GEM_H
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#define TYPE_CADENCE_GEM "cadence_gem"
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#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
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#include "net/net.h"
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#include "hw/sysbus.h"
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#define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
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#define MAX_PRIORITY_QUEUES 8
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#define MAX_TYPE1_SCREENERS 16
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#define MAX_TYPE2_SCREENERS 16
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typedef struct CadenceGEMState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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NICState *nic;
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NICConf conf;
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qemu_irq irq[MAX_PRIORITY_QUEUES];
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/* Static properties */
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uint8_t num_priority_queues;
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uint8_t num_type1_screeners;
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uint8_t num_type2_screeners;
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/* GEM registers backing store */
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uint32_t regs[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are write only */
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uint32_t regs_wo[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are read only */
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uint32_t regs_ro[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are clear on read */
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uint32_t regs_rtc[CADENCE_GEM_MAXREG];
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/* Mask of register bits which are write 1 to clear */
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uint32_t regs_w1c[CADENCE_GEM_MAXREG];
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/* PHY registers backing store */
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uint16_t phy_regs[32];
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uint8_t phy_loop; /* Are we in phy loopback? */
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/* The current DMA descriptor pointers */
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uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
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uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
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uint8_t can_rx_state; /* Debug only */
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unsigned rx_desc[MAX_PRIORITY_QUEUES][2];
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bool sar_active[4];
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} CadenceGEMState;
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#define CADENCE_GEM_H
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#endif
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