5decd2c521
At present the SiFive PLIC model "priority-base" expects interrupt
priority register base starting from source 1 instead source 0,
that's why on most platforms "priority-base" is set to 0x04 except
'opentitan' machine. 'opentitan' should have set "priority-base"
to 0x04 too.
Note the irq number calculation in sifive_plic_{read,write} is
correct as the codes make up for the irq number by adding 1.
Let's simply update "priority-base" to start from interrupt source
0 and add a comment to make it crystal clear.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Message-Id: <20221211030829.802437-14-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/*
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* Shakti C-class SoC emulation
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*
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* Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SHAKTI_C_H
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#define HW_SHAKTI_C_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/boards.h"
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#include "hw/char/shakti_uart.h"
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#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
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#define RISCV_SHAKTI_SOC(obj) \
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OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
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typedef struct ShaktiCSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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DeviceState *plic;
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ShaktiUartState uart;
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MemoryRegion rom;
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} ShaktiCSoCState;
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#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
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#define RISCV_SHAKTI_MACHINE(obj) \
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OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
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typedef struct ShaktiCMachineState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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ShaktiCSoCState soc;
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} ShaktiCMachineState;
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enum {
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SHAKTI_C_ROM,
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SHAKTI_C_RAM,
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SHAKTI_C_UART,
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SHAKTI_C_GPIO,
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SHAKTI_C_PLIC,
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SHAKTI_C_CLINT,
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SHAKTI_C_I2C,
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};
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#define SHAKTI_C_PLIC_HART_CONFIG "MS"
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/* Including Interrupt ID 0 (no interrupt)*/
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#define SHAKTI_C_PLIC_NUM_SOURCES 28
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/* Excluding Priority 0 */
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#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
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#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
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#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
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#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
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#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
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#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
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#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
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#endif
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