qemu-e2k/include/hw/pci/pci_bus.h
Greg Kurz 1c685a9026 pci: Allow PCI bus subtypes to support extended config space accesses
Some PHB implementations, eg. PAPR used on pseries machine, act like
a regular PCI bus rather than a PCIe bus, but allow access to the
PCIe extended config space anyway.

Introduce a new PCI bus class method to modelize this behaviour and
use it when adjusting the config space size limit during accesses.

No behaviour change for existing PCI bus types.

Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <155414130271.574858.4253514266378127489.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-04-09 09:14:47 +10:00

51 lines
1.2 KiB
C

#ifndef QEMU_PCI_BUS_H
#define QEMU_PCI_BUS_H
#include "hw/pci/pci.h"
/*
* PCI Bus datastructures.
*
* Do not access the following members directly;
* use accessor functions in pci.h
*/
typedef struct PCIBusClass {
/*< private >*/
BusClass parent_class;
/*< public >*/
bool (*is_root)(PCIBus *bus);
int (*bus_num)(PCIBus *bus);
uint16_t (*numa_node)(PCIBus *bus);
bool (*allows_extended_config_space)(PCIBus *bus);
} PCIBusClass;
struct PCIBus {
BusState qbus;
PCIIOMMUFunc iommu_fn;
void *iommu_opaque;
uint8_t devfn_min;
uint32_t slot_reserved_mask;
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
pci_route_irq_fn route_intx_to_irq;
void *irq_opaque;
PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
PCIDevice *parent_dev;
MemoryRegion *address_space_mem;
MemoryRegion *address_space_io;
QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
/* The bus IRQ state is the logical OR of the connected devices.
Keep a count of the number of devices with raised IRQs. */
int nirq;
int *irq_count;
Notifier machine_done;
};
#endif /* QEMU_PCI_BUS_H */