qemu-e2k/target/riscv/insn_trans
Nazar Kazakov e972bf22f6 target/riscv: Add Zvkned ISA extension support
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:

* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
[max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11 11:45:55 +10:00
..
trans_privileged.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
trans_rvd.c.inc target/riscv: Update check for Zca/Zcf/Zcd 2023-06-13 17:01:30 +10:00
trans_rvf.c.inc riscv: spelling fixes 2023-09-08 13:08:52 +03:00
trans_rvh.c.inc target/riscv: Handle HLV, HSV via helpers 2023-05-05 10:49:50 +10:00
trans_rvi.c.inc target/riscv: Enable PC-relative translation 2023-06-13 17:37:12 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvv.c.inc target/riscv: Refactor translation of vector-widening instruction 2023-09-11 11:45:55 +10:00
trans_rvvk.c.inc target/riscv: Add Zvkned ISA extension support 2023-09-11 11:45:55 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Enable PC-relative translation 2023-06-13 17:37:12 +10:00
trans_rvzfa.c.inc riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
trans_rvzfh.c.inc riscv: spelling fixes 2023-09-08 13:08:52 +03:00
trans_rvzicbo.c.inc target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00