Richard Henderson ea04dce7bb target/arm: Use tlb_flush_page_bits_by_mmuidx* ... When TBI is enabled in a given regime, 56 bits of the address are significant and we need to clear out any other matching virtual addresses with differing tags. The other uses of tlb_flush_page (without mmuidx) in this file are only used by aarch32 mode. Fixes: 38d931687f Reported-by: Jordan Frank <jordanfrank@fb.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201016210754.818257-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-10-20 16:12:00 +01:00
..
alpha
arm	target/arm: Use tlb_flush_page_bits_by_mmuidx*	2020-10-20 16:12:00 +01:00
avr
cris
hppa
i386	* Drop ninjatool and just require ninja (Paolo)	2020-10-17 20:52:55 +01:00
lm32
m68k
microblaze
mips	target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)	2020-10-17 13:59:40 +02:00
moxie
nios2
openrisc
ppc	ppc: Fix return value in cpu_post_load() error path	2020-10-09 10:15:06 +11:00
riscv	icount: rename functions to be consistent with the module name	2020-10-05 16:41:22 +02:00
rx
s390x
sh4
sparc	target/sparc/int32_helper: Remove duplicated 'Tag Overflow' entry	2020-10-13 13:33:46 +02:00
tilegx
tricore
unicore32
xtensa
meson.build