307 lines
8.3 KiB
C
307 lines
8.3 KiB
C
/*
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* Motorola ColdFire MCF5208 SoC emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licensed under the GPL
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*/
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#include "hw/hw.h"
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#include "hw/m68k/mcf.h"
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#include "qemu/timer.h"
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#include "hw/ptimer.h"
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#include "sysemu/sysemu.h"
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#include "net/net.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "exec/address-spaces.h"
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#define SYS_FREQ 66000000
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#define PCSR_EN 0x0001
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#define PCSR_RLD 0x0002
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#define PCSR_PIF 0x0004
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#define PCSR_PIE 0x0008
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#define PCSR_OVW 0x0010
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#define PCSR_DBG 0x0020
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#define PCSR_DOZE 0x0040
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#define PCSR_PRE_SHIFT 8
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#define PCSR_PRE_MASK 0x0f00
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typedef struct {
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MemoryRegion iomem;
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qemu_irq irq;
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ptimer_state *timer;
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uint16_t pcsr;
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uint16_t pmr;
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uint16_t pcntr;
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} m5208_timer_state;
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static void m5208_timer_update(m5208_timer_state *s)
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{
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if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
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qemu_irq_raise(s->irq);
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else
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qemu_irq_lower(s->irq);
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}
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static void m5208_timer_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque;
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int prescale;
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int limit;
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switch (offset) {
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case 0:
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/* The PIF bit is set-to-clear. */
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if (value & PCSR_PIF) {
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s->pcsr &= ~PCSR_PIF;
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value &= ~PCSR_PIF;
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}
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/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
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if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
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s->pcsr = value;
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m5208_timer_update(s);
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return;
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}
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if (s->pcsr & PCSR_EN)
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ptimer_stop(s->timer);
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s->pcsr = value;
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prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
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ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
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if (s->pcsr & PCSR_RLD)
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limit = s->pmr;
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else
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limit = 0xffff;
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ptimer_set_limit(s->timer, limit, 0);
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if (s->pcsr & PCSR_EN)
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ptimer_run(s->timer, 0);
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break;
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case 2:
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s->pmr = value;
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s->pcsr &= ~PCSR_PIF;
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if ((s->pcsr & PCSR_RLD) == 0) {
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if (s->pcsr & PCSR_OVW)
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ptimer_set_count(s->timer, value);
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} else {
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ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
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}
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break;
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case 4:
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break;
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default:
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hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
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break;
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}
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m5208_timer_update(s);
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}
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static void m5208_timer_trigger(void *opaque)
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque;
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s->pcsr |= PCSR_PIF;
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m5208_timer_update(s);
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}
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static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque;
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switch (addr) {
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case 0:
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return s->pcsr;
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case 2:
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return s->pmr;
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case 4:
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return ptimer_get_count(s->timer);
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default:
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hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
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return 0;
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}
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}
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static const MemoryRegionOps m5208_timer_ops = {
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.read = m5208_timer_read,
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.write = m5208_timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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switch (addr) {
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case 0x110: /* SDCS0 */
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{
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int n;
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for (n = 0; n < 32; n++) {
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if (ram_size < (2u << n))
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break;
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}
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return (n - 1) | 0x40000000;
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}
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case 0x114: /* SDCS1 */
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return 0;
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default:
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hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
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return 0;
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}
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}
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static void m5208_sys_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
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}
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static const MemoryRegionOps m5208_sys_ops = {
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.read = m5208_sys_read,
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.write = m5208_sys_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
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{
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MemoryRegion *iomem = g_new(MemoryRegion, 1);
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m5208_timer_state *s;
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QEMUBH *bh;
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int i;
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/* SDRAMC. */
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memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
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memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
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/* Timers. */
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for (i = 0; i < 2; i++) {
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s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
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bh = qemu_bh_new(m5208_timer_trigger, s);
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s->timer = ptimer_init(bh);
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memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
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"m5208-timer", 0x00004000);
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memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
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&s->iomem);
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s->irq = pic[4 + i];
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}
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}
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static void mcf5208evb_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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M68kCPU *cpu;
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CPUM68KState *env;
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int kernel_size;
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uint64_t elf_entry;
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hwaddr entry;
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qemu_irq *pic;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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if (!cpu_model) {
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cpu_model = "m5208";
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}
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cpu = cpu_m68k_init(cpu_model);
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if (!cpu) {
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fprintf(stderr, "Unable to find m68k CPU definition\n");
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exit(1);
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}
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env = &cpu->env;
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/* Initialize CPU registers. */
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env->vbr = 0;
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/* TODO: Configure BARs. */
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/* DRAM at 0x40000000 */
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memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(address_space_mem, 0x40000000, ram);
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/* Internal SRAM. */
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memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
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vmstate_register_ram_global(sram);
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memory_region_add_subregion(address_space_mem, 0x80000000, sram);
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/* Internal peripherals. */
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pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
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mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
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mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
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mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
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mcf5208_sys_init(address_space_mem, pic);
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if (nb_nics > 1) {
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fprintf(stderr, "Too many NICs\n");
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exit(1);
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}
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if (nd_table[0].used)
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mcf_fec_init(address_space_mem, &nd_table[0],
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0xfc030000, pic + 36);
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/* 0xfc000000 SCM. */
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/* 0xfc004000 XBS. */
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/* 0xfc008000 FlexBus CS. */
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/* 0xfc030000 FEC. */
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/* 0xfc040000 SCM + Power management. */
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/* 0xfc044000 eDMA. */
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/* 0xfc048000 INTC. */
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/* 0xfc058000 I2C. */
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/* 0xfc05c000 QSPI. */
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/* 0xfc060000 UART0. */
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/* 0xfc064000 UART0. */
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/* 0xfc068000 UART0. */
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/* 0xfc070000 DMA timers. */
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/* 0xfc080000 PIT0. */
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/* 0xfc084000 PIT1. */
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/* 0xfc088000 EPORT. */
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/* 0xfc08c000 Watchdog. */
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/* 0xfc090000 clock module. */
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/* 0xfc0a0000 CCM + reset. */
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/* 0xfc0a4000 GPIO. */
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/* 0xfc0a8000 SDRAM controller. */
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/* Load kernel. */
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if (!kernel_filename) {
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fprintf(stderr, "Kernel image must be specified\n");
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exit(1);
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}
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kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
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NULL, NULL, 1, ELF_MACHINE, 0);
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entry = elf_entry;
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if (kernel_size < 0) {
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kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
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}
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename, 0x40000000,
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ram_size);
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entry = 0x40000000;
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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exit(1);
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}
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env->pc = entry;
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}
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static QEMUMachine mcf5208evb_machine = {
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.name = "mcf5208evb",
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.desc = "MCF5206EVB",
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.init = mcf5208evb_init,
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.is_default = 1,
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DEFAULT_MACHINE_OPTIONS,
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};
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static void mcf5208evb_machine_init(void)
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{
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qemu_register_machine(&mcf5208evb_machine);
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}
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machine_init(mcf5208evb_machine_init);
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