74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/*
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* Nuvoton NPCM7xx Flash Interface Unit (FIU)
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_FIU_H
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#define NPCM7XX_FIU_H
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#include "hw/ssi/ssi.h"
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#include "hw/sysbus.h"
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t))
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typedef struct NPCM7xxFIUState NPCM7xxFIUState;
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/**
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* struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
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* @direct_access: Memory region for direct flash access.
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* @fiu: Pointer to flash controller shared state.
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*/
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typedef struct NPCM7xxFIUFlash {
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MemoryRegion direct_access;
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NPCM7xxFIUState *fiu;
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} NPCM7xxFIUFlash;
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/**
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* NPCM7xxFIUState - Device state for one Flash Interface Unit.
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* @parent: System bus device.
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* @mmio: Memory region for register access.
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* @cs_count: Number of flash chips that may be connected to this module.
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* @active_cs: Currently active chip select, or -1 if no chip is selected.
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* @cs_lines: GPIO lines that may be wired to flash chips.
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* @flash: Array of @cs_count per-flash-chip state objects.
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* @spi: The SPI bus mastered by this controller.
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* @regs: Register contents.
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*
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* Each FIU has a shared bank of registers, and controls up to four chip
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* selects. Each chip select has a dedicated memory region which may be used to
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* read and write the flash connected to that chip select as if it were memory.
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*/
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struct NPCM7xxFIUState {
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SysBusDevice parent;
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MemoryRegion mmio;
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int32_t cs_count;
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int32_t active_cs;
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qemu_irq *cs_lines;
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NPCM7xxFIUFlash *flash;
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SSIBus *spi;
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uint32_t regs[NPCM7XX_FIU_NR_REGS];
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};
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#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
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#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
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#endif /* NPCM7XX_FIU_H */
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