551 lines
17 KiB
C
551 lines
17 KiB
C
/*
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* s390x exception / interrupt helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "internal.h"
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#include "qemu/timer.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "hw/s390x/ioinst.h"
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#include "exec/address-spaces.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#endif
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/* #define DEBUG_S390 */
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/* #define DEBUG_S390_STDOUT */
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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if (qemu_log_separate()) { qemu_log(fmt, ##__VA_ARGS__); } } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#if defined(CONFIG_USER_ONLY)
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void s390_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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int rw, int mmu_idx)
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{
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S390CPU *cpu = S390_CPU(cs);
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trigger_pgm_exception(&cpu->env, PGM_ADDRESSING, ILEN_AUTO);
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/* On real machines this value is dropped into LowMem. Since this
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is userland, simply put this someplace that cpu_loop can find it. */
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cpu->env.__excp_addr = address;
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return 1;
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}
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#else /* !CONFIG_USER_ONLY */
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static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
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{
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switch (mmu_idx) {
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case MMU_PRIMARY_IDX:
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return PSW_ASC_PRIMARY;
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case MMU_SECONDARY_IDX:
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return PSW_ASC_SECONDARY;
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case MMU_HOME_IDX:
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return PSW_ASC_HOME;
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default:
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abort();
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}
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}
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int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
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int rw, int mmu_idx)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong vaddr, raddr;
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uint64_t asc;
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int prot;
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DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, orig_vaddr, rw, mmu_idx);
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orig_vaddr &= TARGET_PAGE_MASK;
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vaddr = orig_vaddr;
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if (mmu_idx < MMU_REAL_IDX) {
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asc = cpu_mmu_idx_to_asc(mmu_idx);
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) {
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return 1;
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}
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} else if (mmu_idx == MMU_REAL_IDX) {
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if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) {
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return 1;
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}
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} else {
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abort();
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}
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/* check out of RAM access */
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if (!address_space_access_valid(&address_space_memory, raddr,
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TARGET_PAGE_SIZE, rw)) {
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DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
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(uint64_t)raddr, (uint64_t)ram_size);
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trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
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return 1;
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}
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qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
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__func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
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tlb_set_page(cs, orig_vaddr, raddr, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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static void do_program_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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int ilen = env->int_pgm_ilen;
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if (ilen == ILEN_AUTO) {
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ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
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}
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assert(ilen == 2 || ilen == 4 || ilen == 6);
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switch (env->int_pgm_code) {
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case PGM_PER:
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if (env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION) {
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break;
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}
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/* FALL THROUGH */
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case PGM_OPERATION:
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case PGM_PRIVILEGED:
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case PGM_EXECUTE:
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case PGM_PROTECTION:
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case PGM_ADDRESSING:
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case PGM_SPECIFICATION:
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case PGM_DATA:
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case PGM_FIXPT_OVERFLOW:
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case PGM_FIXPT_DIVIDE:
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case PGM_DEC_OVERFLOW:
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case PGM_DEC_DIVIDE:
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case PGM_HFP_EXP_OVERFLOW:
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case PGM_HFP_EXP_UNDERFLOW:
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case PGM_HFP_SIGNIFICANCE:
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case PGM_HFP_DIVIDE:
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case PGM_TRANS_SPEC:
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case PGM_SPECIAL_OP:
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case PGM_OPERAND:
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case PGM_HFP_SQRT:
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case PGM_PC_TRANS_SPEC:
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case PGM_ALET_SPEC:
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case PGM_MONITOR:
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/* advance the PSW if our exception is not nullifying */
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env->psw.addr += ilen;
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break;
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}
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qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
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__func__, env->int_pgm_code, ilen);
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lowcore = cpu_map_lowcore(env);
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/* Signal PER events with the exception. */
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if (env->per_perc_atmid) {
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env->int_pgm_code |= PGM_PER;
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lowcore->per_address = cpu_to_be64(env->per_address);
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lowcore->per_perc_atmid = cpu_to_be16(env->per_perc_atmid);
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env->per_perc_atmid = 0;
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}
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lowcore->pgm_ilen = cpu_to_be16(ilen);
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lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
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lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->program_new_psw.mask);
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addr = be64_to_cpu(lowcore->program_new_psw.addr);
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lowcore->per_breaking_event_addr = cpu_to_be64(env->gbea);
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cpu_unmap_lowcore(lowcore);
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DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
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env->int_pgm_code, ilen, env->psw.mask,
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env->psw.addr);
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load_psw(env, mask, addr);
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}
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static void do_svc_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->svc_code = cpu_to_be16(env->int_svc_code);
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lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
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lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
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mask = be64_to_cpu(lowcore->svc_new_psw.mask);
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addr = be64_to_cpu(lowcore->svc_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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/* When a PER event is pending, the PER exception has to happen
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immediately after the SERVICE CALL one. */
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if (env->per_perc_atmid) {
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env->int_pgm_code = PGM_PER;
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env->int_pgm_ilen = env->int_svc_ilen;
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do_program_interrupt(env);
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}
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}
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#define VIRTIO_SUBCODE_64 0x0D00
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static void do_ext_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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uint64_t mask, addr;
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uint16_t cpu_addr;
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LowCore *lowcore;
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if (!(env->psw.mask & PSW_MASK_EXT)) {
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cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
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}
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lowcore = cpu_map_lowcore(env);
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if ((env->pending_int & INTERRUPT_EMERGENCY_SIGNAL) &&
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(env->cregs[0] & CR0_EMERGENCY_SIGNAL_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_EMERGENCY);
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cpu_addr = find_first_bit(env->emergency_signals, S390_MAX_CPUS);
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g_assert(cpu_addr < S390_MAX_CPUS);
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lowcore->cpu_addr = cpu_to_be16(cpu_addr);
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clear_bit(cpu_addr, env->emergency_signals);
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if (bitmap_empty(env->emergency_signals, max_cpus)) {
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env->pending_int &= ~INTERRUPT_EMERGENCY_SIGNAL;
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}
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} else if ((env->pending_int & INTERRUPT_EXTERNAL_CALL) &&
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(env->cregs[0] & CR0_EXTERNAL_CALL_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_EXTERNAL_CALL);
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lowcore->cpu_addr = cpu_to_be16(env->external_call_addr);
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env->pending_int &= ~INTERRUPT_EXTERNAL_CALL;
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} else if ((env->pending_int & INTERRUPT_EXT_CLOCK_COMPARATOR) &&
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(env->cregs[0] & CR0_CKC_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_CLOCK_COMP);
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lowcore->cpu_addr = 0;
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env->pending_int &= ~INTERRUPT_EXT_CLOCK_COMPARATOR;
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} else if ((env->pending_int & INTERRUPT_EXT_CPU_TIMER) &&
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(env->cregs[0] & CR0_CPU_TIMER_SC)) {
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lowcore->ext_int_code = cpu_to_be16(EXT_CPU_TIMER);
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lowcore->cpu_addr = 0;
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env->pending_int &= ~INTERRUPT_EXT_CPU_TIMER;
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} else if ((env->pending_int & INTERRUPT_EXT_SERVICE) &&
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(env->cregs[0] & CR0_SERVICE_SC)) {
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/*
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* FIXME: floating IRQs should be considered by all CPUs and
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* shuld not get cleared by CPU reset.
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*/
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lowcore->ext_int_code = cpu_to_be16(EXT_SERVICE);
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lowcore->ext_params = cpu_to_be32(env->service_param);
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lowcore->cpu_addr = 0;
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env->service_param = 0;
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env->pending_int &= ~INTERRUPT_EXT_SERVICE;
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} else {
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g_assert_not_reached();
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}
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mask = be64_to_cpu(lowcore->external_new_psw.mask);
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addr = be64_to_cpu(lowcore->external_new_psw.addr);
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lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
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cpu_unmap_lowcore(lowcore);
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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load_psw(env, mask, addr);
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}
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static void do_io_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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LowCore *lowcore;
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IOIntQueue *q;
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uint8_t isc;
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int disable = 1;
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int found = 0;
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if (!(env->psw.mask & PSW_MASK_IO)) {
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cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
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}
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for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
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uint64_t isc_bits;
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if (env->io_index[isc] < 0) {
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continue;
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}
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if (env->io_index[isc] >= MAX_IO_QUEUE) {
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cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
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isc, env->io_index[isc]);
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}
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q = &env->io_queue[env->io_index[isc]][isc];
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isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
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if (!(env->cregs[6] & isc_bits)) {
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disable = 0;
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continue;
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}
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if (!found) {
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uint64_t mask, addr;
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found = 1;
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lowcore = cpu_map_lowcore(env);
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lowcore->subchannel_id = cpu_to_be16(q->id);
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lowcore->subchannel_nr = cpu_to_be16(q->nr);
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lowcore->io_int_parm = cpu_to_be32(q->parm);
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lowcore->io_int_word = cpu_to_be32(q->word);
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lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->io_new_psw.mask);
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addr = be64_to_cpu(lowcore->io_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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env->io_index[isc]--;
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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load_psw(env, mask, addr);
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}
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if (env->io_index[isc] >= 0) {
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disable = 0;
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}
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continue;
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}
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if (disable) {
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env->pending_int &= ~INTERRUPT_IO;
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}
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}
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static void do_mchk_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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uint64_t mask, addr;
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LowCore *lowcore;
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MchkQueue *q;
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int i;
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if (!(env->psw.mask & PSW_MASK_MCHECK)) {
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cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
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}
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if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) {
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cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
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}
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q = &env->mchk_queue[env->mchk_index];
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if (q->type != 1) {
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/* Don't know how to handle this... */
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cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
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}
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if (!(env->cregs[14] & (1 << 28))) {
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/* CRW machine checks disabled */
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return;
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}
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lowcore = cpu_map_lowcore(env);
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for (i = 0; i < 16; i++) {
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lowcore->floating_pt_save_area[i] = cpu_to_be64(get_freg(env, i)->ll);
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lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
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lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
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lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
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}
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lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
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lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
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lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
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lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
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lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
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lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
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lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
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lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
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lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
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lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
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addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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env->mchk_index--;
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if (env->mchk_index == -1) {
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env->pending_int &= ~INTERRUPT_MCHK;
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}
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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load_psw(env, mask, addr);
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}
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void s390_cpu_do_interrupt(CPUState *cs)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
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__func__, cs->exception_index, env->psw.addr);
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/* handle machine checks */
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if (cs->exception_index == -1 && s390_cpu_has_mcck_int(cpu)) {
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cs->exception_index = EXCP_MCHK;
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}
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/* handle external interrupts */
|
|
if (cs->exception_index == -1 && s390_cpu_has_ext_int(cpu)) {
|
|
cs->exception_index = EXCP_EXT;
|
|
}
|
|
/* handle I/O interrupts */
|
|
if (cs->exception_index == -1 && s390_cpu_has_io_int(cpu)) {
|
|
cs->exception_index = EXCP_IO;
|
|
}
|
|
|
|
switch (cs->exception_index) {
|
|
case EXCP_PGM:
|
|
do_program_interrupt(env);
|
|
break;
|
|
case EXCP_SVC:
|
|
do_svc_interrupt(env);
|
|
break;
|
|
case EXCP_EXT:
|
|
do_ext_interrupt(env);
|
|
break;
|
|
case EXCP_IO:
|
|
do_io_interrupt(env);
|
|
break;
|
|
case EXCP_MCHK:
|
|
do_mchk_interrupt(env);
|
|
break;
|
|
}
|
|
|
|
/* WAIT PSW during interrupt injection */
|
|
if (cs->exception_index == EXCP_HLT) {
|
|
/* don't trigger a cpu_loop_exit(), use an interrupt instead */
|
|
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT);
|
|
}
|
|
cs->exception_index = -1;
|
|
|
|
/* we might still have pending interrupts, but not deliverable */
|
|
if (!env->pending_int) {
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
}
|
|
|
|
bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
if (env->ex_value) {
|
|
/* Execution of the target insn is indivisible from
|
|
the parent EXECUTE insn. */
|
|
return false;
|
|
}
|
|
if (s390_cpu_has_int(cpu)) {
|
|
s390_cpu_do_interrupt(cs);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void s390x_cpu_debug_excp_handler(CPUState *cs)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
|
|
|
|
if (wp_hit && wp_hit->flags & BP_CPU) {
|
|
/* FIXME: When the storage-alteration-space control bit is set,
|
|
the exception should only be triggered if the memory access
|
|
is done using an address space with the storage-alteration-event
|
|
bit set. We have no way to detect that with the current
|
|
watchpoint code. */
|
|
cs->watchpoint_hit = NULL;
|
|
|
|
env->per_address = env->psw.addr;
|
|
env->per_perc_atmid |= PER_CODE_EVENT_STORE | get_per_atmid(env);
|
|
/* FIXME: We currently no way to detect the address space used
|
|
to trigger the watchpoint. For now just consider it is the
|
|
current default ASC. This turn to be true except when MVCP
|
|
and MVCS instrutions are not used. */
|
|
env->per_perc_atmid |= env->psw.mask & (PSW_MASK_ASC) >> 46;
|
|
|
|
/* Remove all watchpoints to re-execute the code. A PER exception
|
|
will be triggered, it will call load_psw which will recompute
|
|
the watchpoints. */
|
|
cpu_watchpoint_remove_all(cs, BP_CPU);
|
|
cpu_loop_exit_noexc(cs);
|
|
}
|
|
}
|
|
|
|
/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
|
|
this is only for the atomic operations, for which we want to raise a
|
|
specification exception. */
|
|
void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
|
MMUAccessType access_type,
|
|
int mmu_idx, uintptr_t retaddr)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
if (retaddr) {
|
|
cpu_restore_state(cs, retaddr);
|
|
}
|
|
program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO);
|
|
}
|
|
|
|
#endif /* CONFIG_USER_ONLY */
|