qemu-e2k/target/openrisc
Stafford Horne dfc84745bb target/openrisc: Fix writes to interrupt mask register
The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits.  Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.

I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.

Reported-by: Davidson Francis <davidsondfgl@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03 22:40:33 +09:00
..
cpu.c linux-user: Implement signals for openrisc 2018-07-03 22:40:33 +09:00
cpu.h target/openrisc: Reorg tlb lookup 2018-07-03 22:40:33 +09:00
disas.c
exception_helper.c
exception.c
exception.h
fpu_helper.c
gdbstub.c
helper.h
insns.decode
interrupt_helper.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00
interrupt.c target/openrisc: Fix delay slot exception flag to match spec 2018-07-03 22:40:33 +09:00
machine.c target/openrisc: Increase the TLB size 2018-07-03 00:05:28 +09:00
Makefile.objs
mmu.c target/openrisc: Reorg tlb lookup 2018-07-03 22:40:33 +09:00
sys_helper.c target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
translate.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00