qemu-e2k/tests/tcg/aarch64
Richard Henderson cda86e2b46 target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17).  The linux kernel
sets this in bti_enable().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220427042312.294300-1-richard.henderson@linaro.org
[PMM: remove stray change to makefile comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05 09:35:50 +01:00
..
gdbstub
system tests/tcg: port SYS_HEAPINFO to a system test 2022-02-28 16:42:42 +00:00
bti-1.c
bti-2.c
bti-3.c target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user 2022-05-05 09:35:50 +01:00
bti-crt.inc.c
fcvt.ref
float_convd.ref tests/tcg: add float_convd test 2022-04-20 16:04:20 +01:00
float_convs.ref
float_madds.ref
Makefile.softmmu-target tests/tcg: add compiler test variables when using containers 2022-04-20 16:04:20 +01:00
Makefile.target target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user 2022-05-05 09:35:50 +01:00
mte-1.c
mte-2.c
mte-3.c
mte-4.c
mte-5.c test/tcg/aarch64: Add mte-5 2021-04-30 11:16:49 +01:00
mte-6.c
mte-7.c target/arm: Fix mte page crossing test 2021-06-16 14:33:51 +01:00
mte.h
pauth-1.c
pauth-2.c
pauth-4.c
pauth-5.c
pcalign-a64.c tests/tcg: Add arm and aarch64 pc alignment tests 2021-12-15 10:35:26 +00:00
semicall.h
sve-ioctls.c
sysregs.c
test-826.c target/arm: Fix sve2 ldnt1 and stnt1 2022-03-18 10:55:15 +00:00