9130cade5f
Convert the Arm CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20221124115023.2437291-3-peter.maydell@linaro.org
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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struct arm_boot_info;
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#define TYPE_ARM_CPU "arm-cpu"
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OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
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#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
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typedef struct ARMCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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void (*class_init)(ObjectClass *oc, void *data);
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} ARMCPUInfo;
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void arm_cpu_register(const ARMCPUInfo *info);
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void aarch64_cpu_register(const ARMCPUInfo *info);
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/**
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* ARMCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* An ARM CPU model.
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*/
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struct ARMCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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const ARMCPUInfo *info;
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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#define TYPE_AARCH64_CPU "aarch64-cpu"
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typedef struct AArch64CPUClass AArch64CPUClass;
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DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
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TYPE_AARCH64_CPU)
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struct AArch64CPUClass {
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/*< private >*/
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ARMCPUClass parent_class;
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/*< public >*/
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};
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void register_cp_regs_for_features(ARMCPU *cpu);
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void init_cpreg_list(ARMCPU *cpu);
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/* Callback functions for the generic timer's timers. */
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void arm_gt_ptimer_cb(void *opaque);
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void arm_gt_vtimer_cb(void *opaque);
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void arm_gt_htimer_cb(void *opaque);
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void arm_gt_stimer_cb(void *opaque);
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void arm_gt_hvtimer_cb(void *opaque);
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#define ARM_AFF0_SHIFT 0
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#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
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#define ARM_AFF1_SHIFT 8
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#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
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#define ARM_AFF2_SHIFT 16
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#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
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#define ARM_AFF3_SHIFT 32
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#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
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#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
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#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
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#define ARM64_AFFINITY_MASK \
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(ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
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#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
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#endif
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