66260159a7
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-11-alex.bennee@linaro.org>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "gdbstub/helpers.h"
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#include "cpu.h"
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#include "internal.h"
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int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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if (n == HEX_REG_P3_0_ALIASED) {
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uint32_t p3_0 = 0;
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for (int i = 0; i < NUM_PREGS; i++) {
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p3_0 = deposit32(p3_0, i * 8, 8, env->pred[i]);
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}
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return gdb_get_regl(mem_buf, p3_0);
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}
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if (n < TOTAL_PER_THREAD_REGS) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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}
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g_assert_not_reached();
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}
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int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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if (n == HEX_REG_P3_0_ALIASED) {
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uint32_t p3_0 = ldtul_p(mem_buf);
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for (int i = 0; i < NUM_PREGS; i++) {
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env->pred[i] = extract32(p3_0, i * 8, 8);
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}
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return sizeof(target_ulong);
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}
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if (n < TOTAL_PER_THREAD_REGS) {
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env->gpr[n] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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}
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g_assert_not_reached();
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}
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static int gdb_get_vreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
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{
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int total = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
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total += gdb_get_regl(mem_buf, env->VRegs[n].uw[i]);
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}
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return total;
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}
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static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n)
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{
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int total = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
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total += gdb_get_regl(mem_buf, env->QRegs[n].uw[i]);
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}
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return total;
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}
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int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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if (n < NUM_VREGS) {
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return gdb_get_vreg(env, mem_buf, n);
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}
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n -= NUM_VREGS;
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if (n < NUM_QREGS) {
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return gdb_get_qreg(env, mem_buf, n);
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}
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g_assert_not_reached();
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}
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static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) {
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env->VRegs[n].uw[i] = ldtul_p(mem_buf);
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mem_buf += 4;
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}
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return MAX_VEC_SIZE_BYTES;
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}
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static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) {
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env->QRegs[n].uw[i] = ldtul_p(mem_buf);
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mem_buf += 4;
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}
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return MAX_VEC_SIZE_BYTES / 8;
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}
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int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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HexagonCPU *cpu = HEXAGON_CPU(cs);
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CPUHexagonState *env = &cpu->env;
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if (n < NUM_VREGS) {
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return gdb_put_vreg(env, mem_buf, n);
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}
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n -= NUM_VREGS;
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if (n < NUM_QREGS) {
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return gdb_put_qreg(env, mem_buf, n);
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}
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g_assert_not_reached();
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}
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