qemu-e2k/target/riscv/insn_trans
LIU Zhiwei ebd476488d target/riscv: Encode the FS and VS on a normal way for tb flags
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.

It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00
..
trans_privileged.c.inc target/riscv: Fix itrigger when icount is used 2023-05-05 10:49:50 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvd.c.inc target/riscv: add support for Zcd extension 2023-05-05 10:49:50 +10:00
trans_rvf.c.inc target/riscv: Encode the FS and VS on a normal way for tb flags 2023-05-05 10:49:50 +10:00
trans_rvh.c.inc target/riscv: Set opcode to env->bins for illegal/virtual instruction fault 2023-05-05 10:49:50 +10:00
trans_rvi.c.inc target/riscv: add support for Zca extension 2023-05-05 10:49:50 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvv.c.inc target/riscv: Encode the FS and VS on a normal way for tb flags 2023-05-05 10:49:50 +10:00
trans_rvzawrs.c.inc RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
trans_rvzce.c.inc target/riscv: remove cpu->cfg.ext_e 2023-05-05 10:49:50 +10:00
trans_rvzfh.c.inc target/riscv: Avoid tcg_const_* 2023-03-05 13:46:13 -08:00
trans_rvzicbo.c.inc target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00