qemu-e2k/hw/arm
Peter Maydell 38848ce565 target-arm queue:
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
  * handle some UNALLOCATED decode cases correctly rather
    than asserting
  * hw: virt: consider hw_compat_6_0
  * hw/arm: add quanta-gbs-bmc machine
  * hw/intc/armv7m_nvic: Remove stale comment
  * target/arm: Fix mte page crossing test
  * hw/arm: quanta-q71l add pca954x muxes
  * target/arm: First few parts of MVE support
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging

target-arm queue:
 * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
 * handle some UNALLOCATED decode cases correctly rather
   than asserting
 * hw: virt: consider hw_compat_6_0
 * hw/arm: add quanta-gbs-bmc machine
 * hw/intc/armv7m_nvic: Remove stale comment
 * target/arm: Fix mte page crossing test
 * hw/arm: quanta-q71l add pca954x muxes
 * target/arm: First few parts of MVE support

# gpg: Signature made Wed 16 Jun 2021 14:34:49 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits)
  include/qemu/int128.h: Add function to create Int128 from int64_t
  bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
  target/arm: Move expand_pred_b() data to vec_helper.c
  target/arm: Add framework for MVE decode
  target/arm: Implement MVE LETP insn
  target/arm: Implement MVE DLSTP
  target/arm: Implement MVE WLSTP insn
  target/arm: Implement MVE LCTP
  target/arm: Let vfp_access_check() handle late NOCP checks
  target/arm: Add handling for PSR.ECI/ICI
  target/arm: Handle VPR semantics in existing code
  target/arm: Enable FPSCR.QC bit for MVE
  target/arm: Provide and use H8 and H1_8 macros
  hw/arm: quanta-q71l add pca954x muxes
  hw/arm: gsj add pca9548
  hw/arm: gsj add i2c comments
  target/arm: Fix mte page crossing test
  hw/intc/armv7m_nvic: Remove stale comment
  hw/arm: quanta-gbs-bmc add i2c comments
  hw/arm: add quanta-gbs-bmc machine
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-16 17:02:30 +01:00
..
allwinner-a10.c
allwinner-h3.c
armsse.c
armv7m.c
aspeed_ast2600.c
aspeed_soc.c
aspeed.c
bcm2835_peripherals.c
bcm2836.c
boot.c
collie.c
cubieboard.c
digic_boards.c
digic.c
exynos4_boards.c
exynos4210.c
fsl-imx6.c
fsl-imx6ul.c
fsl-imx7.c
fsl-imx25.c
fsl-imx31.c
gumstix.c
highbank.c
imx25_pdk.c
integratorcp.c
Kconfig
kzm.c
mainstone.c
mcimx6ul-evk.c
mcimx7d-sabre.c
meson.build
microbit.c
mps2-tz.c
mps2.c
msf2-soc.c
msf2-som.c
musca.c
musicpal.c
netduino2.c
netduinoplus2.c
npcm7xx_boards.c
npcm7xx.c
nrf51_soc.c
nseries.c
omap1.c
omap2.c
omap_sx1.c
orangepi.c
palm.c
pxa2xx_gpio.c
pxa2xx_pic.c
pxa2xx.c
raspi.c
realview.c
sabrelite.c
sbsa-ref.c
smmu-common.c
smmu-internal.h
smmuv3-internal.h
smmuv3.c
spitz.c
stellaris.c
stm32f205_soc.c
stm32f405_soc.c
strongarm.c
strongarm.h
sysbus-fdt.c
tosa.c
trace-events
trace.h
versatilepb.c
vexpress.c
virt-acpi-build.c
virt.c target-arm queue: 2021-06-16 17:02:30 +01:00
xilinx_zynq.c
xlnx-versal-virt.c
xlnx-versal.c
xlnx-zcu102.c
xlnx-zynqmp.c
z2.c