Conor Dooley 592f0a9429 hw/{misc, riscv}: pfsoc: add system controller as unimplemented ... The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221117225518.4102575-4-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
..
Kconfig	hw/riscv: Enable TPM backends	2022-04-29 10:48:48 +10:00
boot.c	riscv: re-randomize rng-seed on reboot	2022-10-27 11:34:31 +01:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/{misc, riscv}: pfsoc: add system controller as unimplemented	2023-01-06 10:42:55 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv/opentitan: add aon_timer base unimpl	2023-01-06 10:42:55 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
sifive_e.c	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	2022-05-24 10:38:50 +10:00
sifive_u.c	hw/riscv: set machine->fdt in sifive_u_machine_init()	2022-10-17 16:15:10 -03:00
spike.c	hw/riscv: set machine->fdt in spike_board_init()	2022-10-17 16:15:10 -03:00
virt.c	hw/riscv: virt: Remove the redundant ipi-id property	2023-01-06 10:42:55 +10:00