qemu-e2k/target/riscv
Alex Bennée 135b03cb9d target/riscv: rationalise softfloat includes
We should avoid including the whole of softfloat headers in cpu.h and
explicitly include it only where we will be calling softfloat
functions. We can use the -types.h and -helpers.h in cpu.h for the few
bits that are global.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Palmer Dabbelt <palmer@sifive.com>
2019-08-19 12:07:13 +01:00
..
insn_trans RISC-V: Clear load reservations on context switch and SC 2019-06-25 22:37:04 -07:00
cpu_bits.h target/riscv: Add the mcountinhibit CSR 2019-06-25 03:05:40 -07:00
cpu_helper.c RISC-V: Clear load reservations on context switch and SC 2019-06-25 22:37:04 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
cpu.h target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
csr.c RISC-V: Add support for the Zicsr extension 2019-06-25 22:32:42 -07:00
fpu_helper.c target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
gdbstub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
helper.h
insn16-32.decode
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode
insn32.decode
instmap.h Supply missing header guards 2019-06-12 13:20:21 +02:00
Makefile.objs
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
pmp.c RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off 2019-06-23 23:44:42 -07:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-06-23 23:44:41 -07:00
trace-events
translate.c RISC-V: Add support for the Zifencei extension 2019-06-25 22:31:21 -07:00