Alistair Francis eccc5a12c2 target/ricsv: Flush the TLB on virtulisation mode changes ... To ensure our TLB isn't out-of-date we flush it on all virt mode changes. Unlike priv mode this isn't saved in the mmu_idx as all guests share V=1. The easiest option is just to flush on all changes. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-02-27 13:45:40 -08:00
..
insn_trans
cpu_bits.h	target/riscv: Add virtual register swapping function	2020-02-27 13:45:35 -08:00
cpu_helper.c	target/ricsv: Flush the TLB on virtulisation mode changes	2020-02-27 13:45:40 -08:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Dump Hypervisor registers if enabled	2020-02-27 13:45:31 -08:00
cpu.h	target/riscv: Add virtual register swapping function	2020-02-27 13:45:35 -08:00
csr.c	target/riscv: Extend the SIP CSR to support virtulisation	2020-02-27 13:45:38 -08:00
fpu_helper.c
gdbstub.c
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
Makefile.objs	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
monitor.c
op_helper.c
pmp.c
pmp.h
trace-events
translate.c