152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
/*
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* OSTimer device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/sysbus.h"
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#include "hw/ptimer.h"
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h"
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/* puv3 ostimer implementation. */
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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QEMUBH *bh;
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qemu_irq irq;
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ptimer_state *ptimer;
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uint32_t reg_OSMR0;
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uint32_t reg_OSCR;
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uint32_t reg_OSSR;
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uint32_t reg_OIER;
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} PUV3OSTState;
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static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PUV3OSTState *s = opaque;
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uint32_t ret = 0;
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switch (offset) {
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case 0x10: /* Counter Register */
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ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
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break;
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case 0x14: /* Status Register */
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ret = s->reg_OSSR;
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break;
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case 0x1c: /* Interrupt Enable Register */
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ret = s->reg_OIER;
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break;
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default:
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DPRINTF("Bad offset %x\n", (int)offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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}
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static void puv3_ost_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PUV3OSTState *s = opaque;
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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switch (offset) {
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case 0x00: /* Match Register 0 */
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s->reg_OSMR0 = value;
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if (s->reg_OSMR0 > s->reg_OSCR) {
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ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
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} else {
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ptimer_set_count(s->ptimer, s->reg_OSMR0 +
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(0xffffffff - s->reg_OSCR));
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}
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ptimer_run(s->ptimer, 2);
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break;
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case 0x14: /* Status Register */
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assert(value == 0);
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if (s->reg_OSSR) {
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s->reg_OSSR = value;
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qemu_irq_lower(s->irq);
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}
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break;
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case 0x1c: /* Interrupt Enable Register */
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s->reg_OIER = value;
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break;
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default:
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DPRINTF("Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps puv3_ost_ops = {
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.read = puv3_ost_read,
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.write = puv3_ost_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void puv3_ost_tick(void *opaque)
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{
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PUV3OSTState *s = opaque;
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DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
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s->reg_OSCR, s->reg_OSMR0);
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s->reg_OSCR = s->reg_OSMR0;
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if (s->reg_OIER) {
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s->reg_OSSR = 1;
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qemu_irq_raise(s->irq);
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}
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}
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static int puv3_ost_init(SysBusDevice *dev)
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{
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PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
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s->reg_OIER = 0;
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s->reg_OSSR = 0;
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s->reg_OSMR0 = 0;
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s->reg_OSCR = 0;
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sysbus_init_irq(dev, &s->irq);
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s->bh = qemu_bh_new(puv3_ost_tick, s);
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s->ptimer = ptimer_init(s->bh);
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ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
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memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
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PUV3_REGS_OFFSET);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void puv3_ost_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = puv3_ost_init;
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}
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static const TypeInfo puv3_ost_info = {
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.name = "puv3_ost",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PUV3OSTState),
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.class_init = puv3_ost_class_init,
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};
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static void puv3_ost_register_type(void)
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{
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type_register_static(&puv3_ost_info);
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}
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type_init(puv3_ost_register_type)
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