3c54cf7705
Generate an interrupt if USR2_RDR and UCR4_DREN are both set. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
109 lines
3.9 KiB
C
109 lines
3.9 KiB
C
/*
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* Device model for i.MX UART
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*
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* Copyright (c) 2008 OKL
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* Originally Written by Hans Jiang
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* Copyright (c) 2011 NICTA Pty Ltd.
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef IMX_SERIAL_H
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#define IMX_SERIAL_H
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#define TYPE_IMX_SERIAL "imx.serial"
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#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
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#define URXD_CHARRDY (1<<15) /* character read is valid */
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#define URXD_ERR (1<<14) /* Character has error */
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#define URXD_FRMERR (1<<12) /* Character has frame error */
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#define URXD_BRK (1<<11) /* Break received */
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#define USR1_PARTYER (1<<15) /* Parity Error */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Tx ready */
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#define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
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#define USR1_ESCF (1<<11) /* Escape sequence interrupt */
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#define USR1_FRAMERR (1<<10) /* Framing error */
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#define USR1_RRDY (1<<9) /* receiver ready */
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#define USR1_AGTIM (1<<8) /* Aging timer interrupt */
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#define USR1_DTRD (1<<7) /* DTR changed */
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#define USR1_RXDS (1<<6) /* Receiver is idle */
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#define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
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#define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
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#define USR2_ADET (1<<15) /* Autobaud complete */
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#define USR2_TXFE (1<<14) /* Transmit FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR/DSR transition */
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#define USR2_IDLE (1<<12) /* UART has been idle for too long */
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#define USR2_ACST (1<<11) /* Autobaud counter stopped */
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#define USR2_RIDELT (1<<10) /* Ring Indicator delta */
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#define USR2_RIIN (1<<9) /* Ring Indicator Input */
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#define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
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#define USR2_WAKE (1<<7) /* Start bit detected */
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#define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */
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#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
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#define USR2_RTSF (1<<4) /* RTS transition */
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#define USR2_TXDC (1<<3) /* Transmission complete */
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#define USR2_BRCD (1<<2) /* Break condition detected */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Receive data ready */
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#define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
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#define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
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#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
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#define UCR1_UARTEN (1<<0) /* UART Enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enable */
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#define UCR2_RXEN (1<<1) /* Receiver enable */
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#define UCR2_SRST (1<<0) /* Reset complete */
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#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
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#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
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#define UTS1_TXEMPTY (1<<6)
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#define UTS1_RXEMPTY (1<<5)
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#define UTS1_TXFULL (1<<4)
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#define UTS1_RXFULL (1<<3)
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typedef struct IMXSerialState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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int32_t readbuff;
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uint32_t usr1;
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uint32_t usr2;
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uint32_t ucr1;
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uint32_t ucr2;
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uint32_t uts1;
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/*
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* The registers below are implemented just so that the
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* guest OS sees what it has written
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*/
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uint32_t onems;
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uint32_t ufcr;
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uint32_t ubmr;
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uint32_t ubrc;
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uint32_t ucr3;
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uint32_t ucr4;
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qemu_irq irq;
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CharBackend chr;
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} IMXSerialState;
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#endif
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