qemu-e2k/target
Peter Maydell ee4402eae1 A misc collection of RISC-V related patches for 3.1.
-----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAluQU38ACgkQIeENKd+X
 cFRAXQgAlhNcwby+Jsk8sbLajMWXEtww9FIv+XESldPOJHmJyCkNDVZX8MuMM7+f
 8NraD3YGDJvXP/BEcmyE5yPC6mx+OIi8ufzqP0rUML1x4+Tpxp8nZ7sBH197RtGg
 eImPA6oKvg4wyfNOrZ+hGa8HF/iMT03TqeKggUPf3dVAs8LV2iUwBIzrRLB4IhIN
 yFnhbcw8cW04tWUhYg4+viDY2k0q7fMrJZkASD/RjGMBjubJkwWvSYOdMIEWSpcG
 2qLT5SohzUzHyKPONsoBKjSIP+nKgtyYR6IJh40FDd5S5RRMHe/n3q9jChIkHMma
 x1eSNvVd41++QlBKqDeAlA+gbdK/uw==
 =FJn/
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging

A misc collection of RISC-V related patches for 3.1.

# gpg: Signature made Wed 05 Sep 2018 23:06:55 BST
# gpg:                using RSA key 21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-pullreq-20180905:
  riscv: remove define cpu_init()
  hw/riscv/spike: Set the soc device tree node as a simple-bus
  hw/riscv/virtio: Set the soc device tree node as a simple-bus
  target/riscv: call gen_goto_tb on DISAS_TOO_MANY
  target/riscv: optimize indirect branches
  target/riscv: optimize cross-page direct jumps in softmmu
  RISC-V: Simplify riscv_cpu_local_irqs_pending
  RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
  RISC-V: Improve page table walker spec compliance
  RISC-V: Update address bits to support sv39 and sv48

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24 16:46:43 +01:00
..
alpha
arm target/arm: Remove a handful of stray tabs 2018-08-24 13:17:48 +01:00
cris
hppa
i386 KVM: cleanup unnecessary #ifdef KVM_CAP_... 2018-08-23 18:46:25 +02:00
lm32
m68k
microblaze
mips target/mips: Add definition of nanoMIPS I7200 CPU 2018-08-24 17:51:59 +02:00
moxie
nios2
openrisc target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
ppc ppc: add DBCR based debugging 2018-08-21 14:28:45 +10:00
riscv riscv: remove define cpu_init() 2018-09-05 09:58:38 -07:00
s390x target/s390x: use regular spaces in translate.c 2018-08-28 17:37:01 +02:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc
tilegx
tricore
unicore32
xtensa target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn 2018-08-06 19:07:21 +01:00