304 lines
8.1 KiB
C
304 lines
8.1 KiB
C
/*
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* QEMU Sparc32 DMA controller emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sparc32_dma.h"
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#include "sun4m.h"
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#include "sysbus.h"
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/* debug DMA */
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//#define DEBUG_DMA
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/*
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* This is the DMA controller part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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*/
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#ifdef DEBUG_DMA
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#define DPRINTF(fmt, ...) \
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do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define DMA_REGS 4
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#define DMA_SIZE (4 * sizeof(uint32_t))
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/* We need the mask, because one instance of the device is not page
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aligned (ledma, start address 0x0010) */
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#define DMA_MASK (DMA_SIZE - 1)
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#define DMA_VER 0xa0000000
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#define DMA_INTR 1
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#define DMA_INTREN 0x10
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#define DMA_WRITE_MEM 0x100
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#define DMA_LOADED 0x04000000
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#define DMA_DRAIN_FIFO 0x40
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#define DMA_RESET 0x80
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typedef struct DMAState DMAState;
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struct DMAState {
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SysBusDevice busdev;
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uint32_t dmaregs[DMA_REGS];
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qemu_irq irq;
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void *iommu;
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qemu_irq dev_reset;
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};
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/* Note: on sparc, the lance 16 bit bus is swapped */
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void ledma_memory_read(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int do_bswap)
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{
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DMAState *s = opaque;
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int i;
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
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addr |= s->dmaregs[3];
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if (do_bswap) {
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sparc_iommu_memory_read(s->iommu, addr, buf, len);
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} else {
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addr &= ~1;
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len &= ~1;
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sparc_iommu_memory_read(s->iommu, addr, buf, len);
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for(i = 0; i < len; i += 2) {
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bswap16s((uint16_t *)(buf + i));
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}
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}
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}
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void ledma_memory_write(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int do_bswap)
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{
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DMAState *s = opaque;
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int l, i;
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uint16_t tmp_buf[32];
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
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addr |= s->dmaregs[3];
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if (do_bswap) {
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sparc_iommu_memory_write(s->iommu, addr, buf, len);
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} else {
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addr &= ~1;
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len &= ~1;
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while (len > 0) {
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l = len;
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if (l > sizeof(tmp_buf))
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l = sizeof(tmp_buf);
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for(i = 0; i < l; i += 2) {
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tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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}
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sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
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len -= l;
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buf += l;
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addr += l;
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}
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}
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}
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static void dma_set_irq(void *opaque, int irq, int level)
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{
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DMAState *s = opaque;
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if (level) {
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DPRINTF("Raise IRQ\n");
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s->dmaregs[0] |= DMA_INTR;
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qemu_irq_raise(s->irq);
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} else {
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s->dmaregs[0] &= ~DMA_INTR;
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq);
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}
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}
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void espdma_memory_read(void *opaque, uint8_t *buf, int len)
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{
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DMAState *s = opaque;
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DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
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sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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s->dmaregs[0] |= DMA_INTR;
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s->dmaregs[1] += len;
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}
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void espdma_memory_write(void *opaque, uint8_t *buf, int len)
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{
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DMAState *s = opaque;
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DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
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sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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s->dmaregs[0] |= DMA_INTR;
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s->dmaregs[1] += len;
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}
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static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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DMAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & DMA_MASK) >> 2;
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DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
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s->dmaregs[saddr]);
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return s->dmaregs[saddr];
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}
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static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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DMAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & DMA_MASK) >> 2;
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DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
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s->dmaregs[saddr], val);
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switch (saddr) {
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case 0:
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if (!(val & DMA_INTREN)) {
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DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq);
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}
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if (val & DMA_RESET) {
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qemu_irq_raise(s->dev_reset);
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qemu_irq_lower(s->dev_reset);
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} else if (val & DMA_DRAIN_FIFO) {
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val &= ~DMA_DRAIN_FIFO;
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} else if (val == 0)
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val = DMA_DRAIN_FIFO;
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val &= 0x0fffffff;
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val |= DMA_VER;
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break;
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case 1:
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s->dmaregs[0] |= DMA_LOADED;
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break;
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default:
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break;
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}
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s->dmaregs[saddr] = val;
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}
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static CPUReadMemoryFunc *dma_mem_read[3] = {
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NULL,
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NULL,
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dma_mem_readl,
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};
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static CPUWriteMemoryFunc *dma_mem_write[3] = {
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NULL,
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NULL,
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dma_mem_writel,
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};
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static void dma_reset(void *opaque)
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{
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DMAState *s = opaque;
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memset(s->dmaregs, 0, DMA_SIZE);
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s->dmaregs[0] = DMA_VER;
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}
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static void dma_save(QEMUFile *f, void *opaque)
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{
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DMAState *s = opaque;
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unsigned int i;
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for (i = 0; i < DMA_REGS; i++)
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qemu_put_be32s(f, &s->dmaregs[i]);
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}
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static int dma_load(QEMUFile *f, void *opaque, int version_id)
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{
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DMAState *s = opaque;
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unsigned int i;
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if (version_id != 2)
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return -EINVAL;
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for (i = 0; i < DMA_REGS; i++)
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qemu_get_be32s(f, &s->dmaregs[i]);
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return 0;
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}
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void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
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{
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DeviceState *dev;
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SysBusDevice *s;
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DMAState *d;
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dev = qdev_create(NULL, "sparc32_dma");
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qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, parent_irq);
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*dev_irq = qdev_get_gpio_in(dev, 0);
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sysbus_mmio_map(s, 0, daddr);
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d = FROM_SYSBUS(DMAState, s);
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*reset = &d->dev_reset;
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return d;
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}
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static void sparc32_dma_init1(SysBusDevice *dev)
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{
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DMAState *s = FROM_SYSBUS(DMAState, dev);
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int dma_io_memory;
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sysbus_init_irq(dev, &s->irq);
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dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
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sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
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register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
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qemu_register_reset(dma_reset, s);
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qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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}
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static SysBusDeviceInfo sparc32_dma_info = {
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.init = sparc32_dma_init1,
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.qdev.name = "sparc32_dma",
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.qdev.size = sizeof(DMAState),
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.qdev.props = (Property[]) {
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{
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.name = "iommu_opaque",
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.info = &qdev_prop_ptr,
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.offset = offsetof(DMAState, iommu),
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},
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{/* end of property list */}
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}
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};
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static void sparc32_dma_register_devices(void)
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{
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sysbus_register_withprop(&sparc32_dma_info);
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}
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device_init(sparc32_dma_register_devices)
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