f55d613bc9
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns
to configure push-pull/open-drain and active-high/active-low
behaviours and thus needs some special handling in the write path.
As some of the capabilities depend on the SoC version a silicon-rev
property is introduced, which is used to guard version-specific
behaviour.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35 lines
745 B
C
35 lines
745 B
C
/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_WDT_H
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#define ASPEED_WDT_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_WDT "aspeed.wdt"
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#define ASPEED_WDT(obj) \
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OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
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#define ASPEED_WDT_REGS_MAX (0x20 / 4)
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typedef struct AspeedWDTState {
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/*< private >*/
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SysBusDevice parent_obj;
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QEMUTimer *timer;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_WDT_REGS_MAX];
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uint32_t pclk_freq;
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uint32_t silicon_rev;
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uint32_t ext_pulse_width_mask;
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} AspeedWDTState;
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#endif /* ASPEED_WDT_H */
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