266 lines
8.2 KiB
C
266 lines
8.2 KiB
C
/*
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* CXL Utility library for devices
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/cxl/cxl.h"
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/*
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* Device registers have no restrictions per the spec, and so fall back to the
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* default memory mapped register rules in 8.2:
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* Software shall use CXL.io Memory Read and Write to access memory mapped
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* register defined in this section. Unless otherwise specified, software
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* shall restrict the accesses width based on the following:
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* • A 32 bit register shall be accessed as a 1 Byte, 2 Bytes or 4 Bytes
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* quantity.
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* • A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4 Bytes or 8
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* Bytes
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* • The address shall be a multiple of the access width, e.g. when
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* accessing a register as a 4 Byte quantity, the address shall be
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* multiple of 4.
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* • The accesses shall map to contiguous bytes.If these rules are not
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* followed, the behavior is undefined
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*/
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static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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if (size == 4) {
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return cxl_dstate->caps_reg_state32[offset / sizeof(*cxl_dstate->caps_reg_state32)];
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} else {
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return cxl_dstate->caps_reg_state64[offset / sizeof(*cxl_dstate->caps_reg_state64)];
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}
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}
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static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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return 0;
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}
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static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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switch (size) {
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case 1:
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return cxl_dstate->mbox_reg_state[offset];
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case 2:
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return cxl_dstate->mbox_reg_state16[offset / size];
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case 4:
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return cxl_dstate->mbox_reg_state32[offset / size];
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case 8:
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return cxl_dstate->mbox_reg_state64[offset / size];
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default:
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g_assert_not_reached();
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}
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}
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static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CTRL:
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/* fallthrough */
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case A_CXL_DEV_MAILBOX_CAP:
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/* RO register */
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CMD:
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break;
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case A_CXL_DEV_BG_CMD_STS:
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/* BG not supported */
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/* fallthrough */
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case A_CXL_DEV_MAILBOX_STS:
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/* Read only register, will get updated by the state machine */
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return;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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if (offset >= A_CXL_DEV_CMD_PAYLOAD) {
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memcpy(cxl_dstate->mbox_reg_state + offset, &value, size);
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return;
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}
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switch (size) {
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case 4:
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mailbox_mem_writel(cxl_dstate->mbox_reg_state32, offset, value);
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break;
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case 8:
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mailbox_mem_writeq(cxl_dstate->mbox_reg_state64, offset, value);
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break;
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default:
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g_assert_not_reached();
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}
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if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
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DOORBELL)) {
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cxl_process_mailbox(cxl_dstate);
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}
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}
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static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint64_t retval = 0;
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retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
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retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1);
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return retval;
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}
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static const MemoryRegionOps mdev_ops = {
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.read = mdev_reg_read,
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.write = NULL, /* memory device register is read only */
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 8,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps mailbox_ops = {
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.read = mailbox_reg_read,
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.write = mailbox_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps dev_ops = {
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.read = dev_reg_read,
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.write = NULL, /* status register is read only */
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps caps_ops = {
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.read = caps_reg_read,
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.write = NULL, /* caps registers are read only */
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate)
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{
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/* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */
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memory_region_init(&cxl_dstate->device_registers, obj, "device-registers",
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pow2ceil(CXL_MMIO_SIZE));
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memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate,
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"cap-array", CXL_CAPS_SIZE);
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memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate,
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"device-status", CXL_DEVICE_STATUS_REGISTERS_LENGTH);
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memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cxl_dstate,
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"mailbox", CXL_MAILBOX_REGISTERS_LENGTH);
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memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops,
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cxl_dstate, "memory device caps",
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CXL_MEMORY_DEVICE_REGISTERS_LENGTH);
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memory_region_add_subregion(&cxl_dstate->device_registers, 0,
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&cxl_dstate->caps);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_DEVICE_STATUS_REGISTERS_OFFSET,
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&cxl_dstate->device);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_MAILBOX_REGISTERS_OFFSET,
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&cxl_dstate->mailbox);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_MEMORY_DEVICE_REGISTERS_OFFSET,
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&cxl_dstate->memory_device);
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}
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static void device_reg_init_common(CXLDeviceState *cxl_dstate) { }
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static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
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{
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/* 2048 payload size, with no interrupt or background support */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
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cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
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}
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static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { }
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void cxl_device_register_init_common(CXLDeviceState *cxl_dstate)
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{
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uint64_t *cap_hdrs = cxl_dstate->caps_reg_state64;
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const int cap_count = 3;
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/* CXL Device Capabilities Array Register */
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ARRAY_FIELD_DP64(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
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ARRAY_FIELD_DP64(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
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ARRAY_FIELD_DP64(cap_hdrs, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
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cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1);
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device_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MAILBOX, 2);
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mailbox_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000);
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memdev_reg_init_common(cxl_dstate);
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assert(cxl_initialize_mailbox(cxl_dstate) == 0);
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}
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