c34ad45992
The test in tests/avocado/machine_loongarch.py is currently failing on big endian hosts like s390x. By comparing the traces between running the QEMU_EFI.fd bios on a s390x and on a x86 host, it's quickly obvious that the CSRRD instruction for the CPUID is behaving differently. And indeed: The code currently does a long read (i.e. 64 bit) from the address that points to the CPUState->cpu_index field (with tcg_gen_ld_tl() in the trans_csrrd() function). But this cpu_index field is only an "int" (i.e. 32 bit). While this dirty pointer magic works on little endian hosts, it of course fails on big endian hosts. Fix it by using a proper helper function instead. Message-Id: <20230720175307.854460-1-thuth@redhat.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Thomas Huth <thuth@redhat.com>
98 lines
2.1 KiB
C
98 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch emulation helpers for CSRs
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "internals.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "hw/irq.h"
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#include "cpu-csr.h"
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target_ulong helper_csrrd_pgd(CPULoongArchState *env)
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{
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int64_t v;
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if (env->CSR_TLBRERA & 0x1) {
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v = env->CSR_TLBRBADV;
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} else {
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v = env->CSR_BADV;
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}
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if ((v >> 63) & 0x1) {
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v = env->CSR_PGDH;
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} else {
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v = env->CSR_PGDL;
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}
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return v;
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}
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target_ulong helper_csrrd_cpuid(CPULoongArchState *env)
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{
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LoongArchCPU *lac = env_archcpu(env);
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env->CSR_CPUID = CPU(lac)->cpu_index;
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return env->CSR_CPUID;
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}
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target_ulong helper_csrrd_tval(CPULoongArchState *env)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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return cpu_loongarch_get_constant_timer_ticks(cpu);
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}
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target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
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{
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int64_t old_v = env->CSR_ESTAT;
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/* Only IS[1:0] can be written */
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env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);
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return old_v;
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}
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target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
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{
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int64_t old_v = env->CSR_ASID;
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/* Only ASID filed of CSR_ASID can be written */
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env->CSR_ASID = deposit64(env->CSR_ASID, 0, 10, val);
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if (old_v != env->CSR_ASID) {
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tlb_flush(env_cpu(env));
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}
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return old_v;
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}
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target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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int64_t old_v = env->CSR_TCFG;
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cpu_loongarch_store_constant_timer_config(cpu, val);
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return old_v;
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}
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target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
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{
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LoongArchCPU *cpu = env_archcpu(env);
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int64_t old_v = 0;
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if (val & 0x1) {
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qemu_mutex_lock_iothread();
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loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0);
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qemu_mutex_unlock_iothread();
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}
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return old_v;
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}
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