b71d0385e9
In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/*
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* Allwinner H3 SDRAM Controller emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
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#define HW_MISC_ALLWINNER_H3_DRAMC_H
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#include "qom/object.h"
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#include "hw/sysbus.h"
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#include "exec/hwaddr.h"
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/**
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* Constants
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* @{
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*/
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/** Highest register address used by DRAMCOM module */
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#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
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/** Total number of known DRAMCOM registers */
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#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMCTL module */
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#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
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/** Total number of known DRAMCTL registers */
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#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** Highest register address used by DRAMPHY module */
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#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
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/** Total number of known DRAMPHY registers */
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#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
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sizeof(uint32_t))
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/** @} */
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/**
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* Object model
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* @{
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*/
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#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
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#define AW_H3_DRAMC(obj) \
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OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
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/** @} */
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/**
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* Allwinner H3 SDRAM Controller object instance state.
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*/
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typedef struct AwH3DramCtlState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/** Physical base address for start of RAM */
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hwaddr ram_addr;
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/** Total RAM size in megabytes */
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uint32_t ram_size;
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/**
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* @name Memory Regions
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* @{
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*/
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MemoryRegion row_mirror; /**< Simulates rows for RAM size detection */
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MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored */
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MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
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MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
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MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
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/** @} */
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/**
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* @name Hardware Registers
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* @{
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*/
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uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM registers */
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uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL registers */
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uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY registers */
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/** @} */
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} AwH3DramCtlState;
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#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
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