0a78d7ebf8
The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/*
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* ARM IoT Kit security controller
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the security controller which is part of the
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* Arm IoT Kit and documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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*
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* QEMU interface:
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* + sysbus MMIO region 0 is the "secure privilege control block" registers
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* + sysbus MMIO region 1 is the "non-secure privilege control block" registers
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* + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
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* should RAZ/WI or bus error
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* + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
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* + named GPIO output "msc_irq" for the combined IRQ line from the MSCs
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* Controlling the 2 APB PPCs in the IoTKit:
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* + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
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* + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
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* + named GPIO outputs apb_ppc{0,1}_irq_enable
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* + named GPIO outputs apb_ppc{0,1}_irq_clear
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* + named GPIO inputs apb_ppc{0,1}_irq_status
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* Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling the (up to) 4 MPCs in the IoTKit/SSE:
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* + named GPIO inputs mpc_status[0..3]
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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* Controlling each of the 16 expansion MSCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mscexp_status[0..15]
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* + named GPIO outputs mscexp_clear[0..15]
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* + named GPIO outputs mscexp_ns[0..15]
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*/
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#ifndef IOTKIT_SECCTL_H
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#define IOTKIT_SECCTL_H
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#include "hw/sysbus.h"
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#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
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#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL)
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#define IOTS_APB_PPC0_NUM_PORTS 3
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#define IOTS_APB_PPC1_NUM_PORTS 1
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#define IOTS_PPC_NUM_PORTS 16
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#define IOTS_NUM_APB_PPC 2
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#define IOTS_NUM_APB_EXP_PPC 4
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#define IOTS_NUM_AHB_EXP_PPC 4
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#define IOTS_NUM_EXP_MPC 16
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#define IOTS_NUM_MPC 4
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#define IOTS_NUM_EXP_MSC 16
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typedef struct IoTKitSecCtl IoTKitSecCtl;
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/* State and IRQ lines relating to a PPC. For the
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* PPCs in the IoTKit not all the IRQ lines are used.
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*/
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typedef struct IoTKitSecCtlPPC {
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qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
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qemu_irq ap[IOTS_PPC_NUM_PORTS];
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qemu_irq irq_enable;
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qemu_irq irq_clear;
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uint32_t ns;
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uint32_t sp;
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uint32_t nsp;
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/* Number of ports actually present */
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int numports;
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/* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
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int irq_bit_offset;
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IoTKitSecCtl *parent;
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} IoTKitSecCtlPPC;
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struct IoTKitSecCtl {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq sec_resp_cfg;
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qemu_irq nsc_cfg_irq;
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MemoryRegion s_regs;
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MemoryRegion ns_regs;
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uint32_t secppcintstat;
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uint32_t secppcinten;
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uint32_t secrespcfg;
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uint32_t nsccfg;
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uint32_t brginten;
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uint32_t mpcintstatus;
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uint32_t secmscintstat;
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uint32_t secmscinten;
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uint32_t nsmscexp;
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qemu_irq mscexp_clear[IOTS_NUM_EXP_MSC];
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qemu_irq mscexp_ns[IOTS_NUM_EXP_MSC];
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qemu_irq msc_irq;
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IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
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IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
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IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
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};
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#endif
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