778 lines
26 KiB
C
778 lines
26 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2019 Red Hat, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qemu/cutils.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "qapi/qapi-visit-common.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/cpus.h"
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#include "sysemu/numa.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "acpi-microvm.h"
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#include "hw/loader.h"
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#include "hw/irq.h"
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#include "hw/kvm/clock.h"
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#include "hw/i386/microvm.h"
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#include "hw/i386/x86.h"
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#include "target/i386/cpu.h"
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#include "hw/intc/i8259.h"
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#include "hw/timer/i8254.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/char/serial.h"
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#include "hw/display/ramfb.h"
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#include "hw/i386/topology.h"
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#include "hw/i386/e820_memory_layout.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/virtio/virtio-mmio.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/generic_event_device.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/usb/xhci.h"
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#include "elf.h"
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#include "kvm/kvm_i386.h"
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#include "hw/xen/start_info.h"
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#define MICROVM_QBOOT_FILENAME "qboot.rom"
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#define MICROVM_BIOS_FILENAME "bios-microvm.bin"
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static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s)
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{
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X86MachineState *x86ms = X86_MACHINE(mms);
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int val;
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val = MIN(x86ms->below_4g_mem_size / KiB, 640);
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rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8);
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/* extended memory (next 64MiB) */
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if (x86ms->below_4g_mem_size > 1 * MiB) {
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val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
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} else {
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val = 0;
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}
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if (val > 65535) {
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val = 65535;
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}
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8);
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8);
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/* memory between 16MiB and 4GiB */
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if (x86ms->below_4g_mem_size > 16 * MiB) {
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val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
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} else {
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val = 0;
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}
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if (val > 65535) {
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val = 65535;
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}
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8);
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/* memory above 4GiB */
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val = x86ms->above_4g_mem_size / 65536;
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rtc_set_memory(s, 0x5b, val);
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rtc_set_memory(s, 0x5c, val >> 8);
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rtc_set_memory(s, 0x5d, val >> 16);
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}
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static void create_gpex(MicrovmMachineState *mms)
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{
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X86MachineState *x86ms = X86_MACHINE(mms);
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MemoryRegion *mmio32_alias;
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MemoryRegion *mmio64_alias;
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MemoryRegion *mmio_reg;
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MemoryRegion *ecam_alias;
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MemoryRegion *ecam_reg;
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DeviceState *dev;
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int i;
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dev = qdev_new(TYPE_GPEX_HOST);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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/* Map only the first size_ecam bytes of ECAM space */
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
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ecam_reg, 0, mms->gpex.ecam.size);
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memory_region_add_subregion(get_system_memory(),
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mms->gpex.ecam.base, ecam_alias);
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/* Map the MMIO window into system address space so as to expose
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* the section of PCI MMIO space which starts at the same base address
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* (ie 1:1 mapping for that part of PCI MMIO space visible through
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* the window).
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*/
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mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
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if (mms->gpex.mmio32.size) {
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mmio32_alias = g_new0(MemoryRegion, 1);
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memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg,
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mms->gpex.mmio32.base, mms->gpex.mmio32.size);
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memory_region_add_subregion(get_system_memory(),
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mms->gpex.mmio32.base, mmio32_alias);
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}
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if (mms->gpex.mmio64.size) {
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mmio64_alias = g_new0(MemoryRegion, 1);
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memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg,
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mms->gpex.mmio64.base, mms->gpex.mmio64.size);
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memory_region_add_subregion(get_system_memory(),
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mms->gpex.mmio64.base, mmio64_alias);
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}
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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x86ms->gsi[mms->gpex.irq + i]);
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}
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}
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static int microvm_ioapics(MicrovmMachineState *mms)
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{
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if (!x86_machine_is_acpi_enabled(X86_MACHINE(mms))) {
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return 1;
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}
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if (mms->ioapic2 == ON_OFF_AUTO_OFF) {
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return 1;
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}
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return 2;
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}
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static void microvm_devices_init(MicrovmMachineState *mms)
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{
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const char *default_firmware;
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X86MachineState *x86ms = X86_MACHINE(mms);
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ISABus *isa_bus;
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ISADevice *rtc_state;
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GSIState *gsi_state;
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int ioapics;
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int i;
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/* Core components */
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ioapics = microvm_ioapics(mms);
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gsi_state = g_malloc0(sizeof(*gsi_state));
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x86ms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state,
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IOAPIC_NUM_PINS * ioapics);
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isa_bus = isa_bus_new(NULL, get_system_memory(), get_system_io(),
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&error_abort);
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isa_bus_irqs(isa_bus, x86ms->gsi);
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ioapic_init_gsi(gsi_state, "machine");
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if (ioapics > 1) {
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x86ms->ioapic2 = ioapic_init_secondary(gsi_state);
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}
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kvmclock_create(true);
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mms->virtio_irq_base = 5;
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mms->virtio_num_transports = 8;
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if (x86ms->ioapic2) {
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mms->pcie_irq_base = 16; /* 16 -> 19 */
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/* use second ioapic (24 -> 47) for virtio-mmio irq lines */
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mms->virtio_irq_base = IO_APIC_SECONDARY_IRQBASE;
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mms->virtio_num_transports = IOAPIC_NUM_PINS;
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} else if (x86_machine_is_acpi_enabled(x86ms)) {
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mms->pcie_irq_base = 12; /* 12 -> 15 */
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mms->virtio_irq_base = 16; /* 16 -> 23 */
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}
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for (i = 0; i < mms->virtio_num_transports; i++) {
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sysbus_create_simple("virtio-mmio",
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VIRTIO_MMIO_BASE + i * 512,
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x86ms->gsi[mms->virtio_irq_base + i]);
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}
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/* Optional and legacy devices */
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if (x86_machine_is_acpi_enabled(x86ms)) {
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DeviceState *dev = qdev_new(TYPE_ACPI_GED_X86);
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qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE);
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/* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, GED_MMIO_BASE_REGS);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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x86ms->gsi[GED_MMIO_IRQ]);
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sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
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x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
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}
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if (x86_machine_is_acpi_enabled(x86ms) && machine_usb(MACHINE(mms))) {
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DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
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qdev_prop_set_uint32(dev, "intrs", 1);
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qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
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qdev_prop_set_uint32(dev, "p2", 8);
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qdev_prop_set_uint32(dev, "p3", 8);
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sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MICROVM_XHCI_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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x86ms->gsi[MICROVM_XHCI_IRQ]);
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}
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if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
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/* use topmost 25% of the address space available */
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hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
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if (phys_size > 0x1000000ll) {
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mms->gpex.mmio64.size = phys_size / 4;
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mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
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}
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mms->gpex.mmio32.base = PCIE_MMIO_BASE;
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mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
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mms->gpex.ecam.base = PCIE_ECAM_BASE;
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mms->gpex.ecam.size = PCIE_ECAM_SIZE;
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mms->gpex.irq = mms->pcie_irq_base;
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create_gpex(mms);
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x86ms->pci_irq_mask = ((1 << (mms->pcie_irq_base + 0)) |
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(1 << (mms->pcie_irq_base + 1)) |
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(1 << (mms->pcie_irq_base + 2)) |
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(1 << (mms->pcie_irq_base + 3)));
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} else {
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x86ms->pci_irq_mask = 0;
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}
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if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
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qemu_irq *i8259;
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i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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gsi_state->i8259_irq[i] = i8259[i];
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}
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g_free(i8259);
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}
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if (mms->pit == ON_OFF_AUTO_ON || mms->pit == ON_OFF_AUTO_AUTO) {
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if (kvm_pit_in_kernel()) {
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kvm_pit_init(isa_bus, 0x40);
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} else {
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i8254_pit_init(isa_bus, 0x40, 0, NULL);
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}
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}
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if (mms->rtc == ON_OFF_AUTO_ON ||
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(mms->rtc == ON_OFF_AUTO_AUTO && !kvm_enabled())) {
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rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
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microvm_set_rtc(mms, rtc_state);
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}
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if (mms->isa_serial) {
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serial_hds_isa_init(isa_bus, 0, 1);
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}
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default_firmware = x86_machine_is_acpi_enabled(x86ms)
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? MICROVM_BIOS_FILENAME
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: MICROVM_QBOOT_FILENAME;
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x86_bios_rom_init(MACHINE(mms), default_firmware, get_system_memory(), true);
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}
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static void microvm_memory_init(MicrovmMachineState *mms)
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{
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MachineState *machine = MACHINE(mms);
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X86MachineState *x86ms = X86_MACHINE(mms);
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MemoryRegion *ram_below_4g, *ram_above_4g;
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MemoryRegion *system_memory = get_system_memory();
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FWCfgState *fw_cfg;
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ram_addr_t lowmem = 0xc0000000; /* 3G */
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int i;
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if (machine->ram_size > lowmem) {
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x86ms->above_4g_mem_size = machine->ram_size - lowmem;
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x86ms->below_4g_mem_size = lowmem;
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} else {
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x86ms->above_4g_mem_size = 0;
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x86ms->below_4g_mem_size = machine->ram_size;
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}
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ram_below_4g = g_malloc(sizeof(*ram_below_4g));
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memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
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0, x86ms->below_4g_mem_size);
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memory_region_add_subregion(system_memory, 0, ram_below_4g);
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e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
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if (x86ms->above_4g_mem_size > 0) {
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ram_above_4g = g_malloc(sizeof(*ram_above_4g));
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memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
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machine->ram,
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x86ms->below_4g_mem_size,
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x86ms->above_4g_mem_size);
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memory_region_add_subregion(system_memory, 0x100000000ULL,
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ram_above_4g);
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e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
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}
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fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
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&address_space_memory);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
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fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
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fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
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&e820_reserve, sizeof(e820_reserve));
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fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
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sizeof(struct e820_entry) * e820_get_num_entries());
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rom_set_fw(fw_cfg);
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if (machine->kernel_filename != NULL) {
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x86_load_linux(x86ms, fw_cfg, 0, true);
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}
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if (mms->option_roms) {
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for (i = 0; i < nb_option_roms; i++) {
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rom_add_option(option_rom[i].name, option_rom[i].bootindex);
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}
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}
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x86ms->fw_cfg = fw_cfg;
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x86ms->ioapic_as = &address_space_memory;
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}
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static gchar *microvm_get_mmio_cmdline(gchar *name, uint32_t virtio_irq_base)
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{
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gchar *cmdline;
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gchar *separator;
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long int index;
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int ret;
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separator = g_strrstr(name, ".");
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if (!separator) {
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return NULL;
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}
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if (qemu_strtol(separator + 1, NULL, 10, &index) != 0) {
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return NULL;
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}
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cmdline = g_malloc0(VIRTIO_CMDLINE_MAXLEN);
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ret = g_snprintf(cmdline, VIRTIO_CMDLINE_MAXLEN,
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" virtio_mmio.device=512@0x%lx:%ld",
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VIRTIO_MMIO_BASE + index * 512,
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virtio_irq_base + index);
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if (ret < 0 || ret >= VIRTIO_CMDLINE_MAXLEN) {
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g_free(cmdline);
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return NULL;
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}
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return cmdline;
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}
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static void microvm_fix_kernel_cmdline(MachineState *machine)
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{
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X86MachineState *x86ms = X86_MACHINE(machine);
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MicrovmMachineState *mms = MICROVM_MACHINE(machine);
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BusState *bus;
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BusChild *kid;
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char *cmdline;
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/*
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* Find MMIO transports with attached devices, and add them to the kernel
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* command line.
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*
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* Yes, this is a hack, but one that heavily improves the UX without
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* introducing any significant issues.
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*/
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cmdline = g_strdup(machine->kernel_cmdline);
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bus = sysbus_get_default();
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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DeviceState *dev = kid->child;
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ObjectClass *class = object_get_class(OBJECT(dev));
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if (class == object_class_by_name(TYPE_VIRTIO_MMIO)) {
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VirtIOMMIOProxy *mmio = VIRTIO_MMIO(OBJECT(dev));
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VirtioBusState *mmio_virtio_bus = &mmio->bus;
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BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
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if (!QTAILQ_EMPTY(&mmio_bus->children)) {
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gchar *mmio_cmdline = microvm_get_mmio_cmdline
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(mmio_bus->name, mms->virtio_irq_base);
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if (mmio_cmdline) {
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char *newcmd = g_strjoin(NULL, cmdline, mmio_cmdline, NULL);
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g_free(mmio_cmdline);
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g_free(cmdline);
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cmdline = newcmd;
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}
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}
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}
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}
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fw_cfg_modify_i32(x86ms->fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(cmdline) + 1);
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fw_cfg_modify_string(x86ms->fw_cfg, FW_CFG_CMDLINE_DATA, cmdline);
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g_free(cmdline);
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}
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|
static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
X86CPU *cpu = X86_CPU(dev);
|
|
|
|
cpu->host_phys_bits = true; /* need reliable phys-bits */
|
|
x86_cpu_pre_plug(hotplug_dev, dev, errp);
|
|
}
|
|
|
|
static void microvm_device_plug_cb(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
x86_cpu_plug(hotplug_dev, dev, errp);
|
|
}
|
|
|
|
static void microvm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
error_setg(errp, "unplug not supported by microvm");
|
|
}
|
|
|
|
static void microvm_device_unplug_cb(HotplugHandler *hotplug_dev,
|
|
DeviceState *dev, Error **errp)
|
|
{
|
|
error_setg(errp, "unplug not supported by microvm");
|
|
}
|
|
|
|
static HotplugHandler *microvm_get_hotplug_handler(MachineState *machine,
|
|
DeviceState *dev)
|
|
{
|
|
if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
|
|
return HOTPLUG_HANDLER(machine);
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
static void microvm_machine_state_init(MachineState *machine)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(machine);
|
|
X86MachineState *x86ms = X86_MACHINE(machine);
|
|
|
|
microvm_memory_init(mms);
|
|
|
|
x86_cpus_init(x86ms, CPU_VERSION_LATEST);
|
|
|
|
microvm_devices_init(mms);
|
|
}
|
|
|
|
static void microvm_machine_reset(MachineState *machine)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(machine);
|
|
CPUState *cs;
|
|
X86CPU *cpu;
|
|
|
|
if (!x86_machine_is_acpi_enabled(X86_MACHINE(machine)) &&
|
|
machine->kernel_filename != NULL &&
|
|
mms->auto_kernel_cmdline && !mms->kernel_cmdline_fixed) {
|
|
microvm_fix_kernel_cmdline(machine);
|
|
mms->kernel_cmdline_fixed = true;
|
|
}
|
|
|
|
qemu_devices_reset();
|
|
|
|
CPU_FOREACH(cs) {
|
|
cpu = X86_CPU(cs);
|
|
|
|
if (cpu->apic_state) {
|
|
device_legacy_reset(cpu->apic_state);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void microvm_machine_get_pic(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
OnOffAuto pic = mms->pic;
|
|
|
|
visit_type_OnOffAuto(v, name, &pic, errp);
|
|
}
|
|
|
|
static void microvm_machine_set_pic(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
visit_type_OnOffAuto(v, name, &mms->pic, errp);
|
|
}
|
|
|
|
static void microvm_machine_get_pit(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
OnOffAuto pit = mms->pit;
|
|
|
|
visit_type_OnOffAuto(v, name, &pit, errp);
|
|
}
|
|
|
|
static void microvm_machine_set_pit(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
visit_type_OnOffAuto(v, name, &mms->pit, errp);
|
|
}
|
|
|
|
static void microvm_machine_get_rtc(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
OnOffAuto rtc = mms->rtc;
|
|
|
|
visit_type_OnOffAuto(v, name, &rtc, errp);
|
|
}
|
|
|
|
static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
visit_type_OnOffAuto(v, name, &mms->rtc, errp);
|
|
}
|
|
|
|
static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
OnOffAuto pcie = mms->pcie;
|
|
|
|
visit_type_OnOffAuto(v, name, &pcie, errp);
|
|
}
|
|
|
|
static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
visit_type_OnOffAuto(v, name, &mms->pcie, errp);
|
|
}
|
|
|
|
static void microvm_machine_get_ioapic2(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
OnOffAuto ioapic2 = mms->ioapic2;
|
|
|
|
visit_type_OnOffAuto(v, name, &ioapic2, errp);
|
|
}
|
|
|
|
static void microvm_machine_set_ioapic2(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
visit_type_OnOffAuto(v, name, &mms->ioapic2, errp);
|
|
}
|
|
|
|
static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
return mms->isa_serial;
|
|
}
|
|
|
|
static void microvm_machine_set_isa_serial(Object *obj, bool value,
|
|
Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
mms->isa_serial = value;
|
|
}
|
|
|
|
static bool microvm_machine_get_option_roms(Object *obj, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
return mms->option_roms;
|
|
}
|
|
|
|
static void microvm_machine_set_option_roms(Object *obj, bool value,
|
|
Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
mms->option_roms = value;
|
|
}
|
|
|
|
static bool microvm_machine_get_auto_kernel_cmdline(Object *obj, Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
return mms->auto_kernel_cmdline;
|
|
}
|
|
|
|
static void microvm_machine_set_auto_kernel_cmdline(Object *obj, bool value,
|
|
Error **errp)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
mms->auto_kernel_cmdline = value;
|
|
}
|
|
|
|
static void microvm_machine_done(Notifier *notifier, void *data)
|
|
{
|
|
MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
|
|
machine_done);
|
|
|
|
acpi_setup_microvm(mms);
|
|
}
|
|
|
|
static void microvm_powerdown_req(Notifier *notifier, void *data)
|
|
{
|
|
MicrovmMachineState *mms = container_of(notifier, MicrovmMachineState,
|
|
powerdown_req);
|
|
X86MachineState *x86ms = X86_MACHINE(mms);
|
|
|
|
if (x86ms->acpi_dev) {
|
|
Object *obj = OBJECT(x86ms->acpi_dev);
|
|
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(obj);
|
|
adevc->send_event(ACPI_DEVICE_IF(x86ms->acpi_dev),
|
|
ACPI_POWER_DOWN_STATUS);
|
|
}
|
|
}
|
|
|
|
static void microvm_machine_initfn(Object *obj)
|
|
{
|
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
|
|
|
/* Configuration */
|
|
mms->pic = ON_OFF_AUTO_AUTO;
|
|
mms->pit = ON_OFF_AUTO_AUTO;
|
|
mms->rtc = ON_OFF_AUTO_AUTO;
|
|
mms->pcie = ON_OFF_AUTO_AUTO;
|
|
mms->ioapic2 = ON_OFF_AUTO_AUTO;
|
|
mms->isa_serial = true;
|
|
mms->option_roms = true;
|
|
mms->auto_kernel_cmdline = true;
|
|
|
|
/* State */
|
|
mms->kernel_cmdline_fixed = false;
|
|
|
|
mms->machine_done.notify = microvm_machine_done;
|
|
qemu_add_machine_init_done_notifier(&mms->machine_done);
|
|
mms->powerdown_req.notify = microvm_powerdown_req;
|
|
qemu_register_powerdown_notifier(&mms->powerdown_req);
|
|
}
|
|
|
|
static void microvm_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
|
|
|
|
mc->init = microvm_machine_state_init;
|
|
|
|
mc->family = "microvm_i386";
|
|
mc->desc = "microvm (i386)";
|
|
mc->units_per_default_bus = 1;
|
|
mc->no_floppy = 1;
|
|
mc->max_cpus = 288;
|
|
mc->has_hotpluggable_cpus = false;
|
|
mc->auto_enable_numa_with_memhp = false;
|
|
mc->auto_enable_numa_with_memdev = false;
|
|
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
|
|
mc->nvdimm_supported = false;
|
|
mc->default_ram_id = "microvm.ram";
|
|
|
|
/* Avoid relying too much on kernel components */
|
|
mc->default_kernel_irqchip_split = true;
|
|
|
|
/* Machine class handlers */
|
|
mc->reset = microvm_machine_reset;
|
|
|
|
/* hotplug (for cpu coldplug) */
|
|
mc->get_hotplug_handler = microvm_get_hotplug_handler;
|
|
hc->pre_plug = microvm_device_pre_plug_cb;
|
|
hc->plug = microvm_device_plug_cb;
|
|
hc->unplug_request = microvm_device_unplug_request_cb;
|
|
hc->unplug = microvm_device_unplug_cb;
|
|
|
|
x86mc->fwcfg_dma_enabled = true;
|
|
|
|
object_class_property_add(oc, MICROVM_MACHINE_PIC, "OnOffAuto",
|
|
microvm_machine_get_pic,
|
|
microvm_machine_set_pic,
|
|
NULL, NULL);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_PIC,
|
|
"Enable i8259 PIC");
|
|
|
|
object_class_property_add(oc, MICROVM_MACHINE_PIT, "OnOffAuto",
|
|
microvm_machine_get_pit,
|
|
microvm_machine_set_pit,
|
|
NULL, NULL);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_PIT,
|
|
"Enable i8254 PIT");
|
|
|
|
object_class_property_add(oc, MICROVM_MACHINE_RTC, "OnOffAuto",
|
|
microvm_machine_get_rtc,
|
|
microvm_machine_set_rtc,
|
|
NULL, NULL);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
|
|
"Enable MC146818 RTC");
|
|
|
|
object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto",
|
|
microvm_machine_get_pcie,
|
|
microvm_machine_set_pcie,
|
|
NULL, NULL);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_PCIE,
|
|
"Enable PCIe");
|
|
|
|
object_class_property_add(oc, MICROVM_MACHINE_IOAPIC2, "OnOffAuto",
|
|
microvm_machine_get_ioapic2,
|
|
microvm_machine_set_ioapic2,
|
|
NULL, NULL);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_IOAPIC2,
|
|
"Enable second IO-APIC");
|
|
|
|
object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
|
|
microvm_machine_get_isa_serial,
|
|
microvm_machine_set_isa_serial);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_ISA_SERIAL,
|
|
"Set off to disable the instantiation an ISA serial port");
|
|
|
|
object_class_property_add_bool(oc, MICROVM_MACHINE_OPTION_ROMS,
|
|
microvm_machine_get_option_roms,
|
|
microvm_machine_set_option_roms);
|
|
object_class_property_set_description(oc, MICROVM_MACHINE_OPTION_ROMS,
|
|
"Set off to disable loading option ROMs");
|
|
|
|
object_class_property_add_bool(oc, MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
|
|
microvm_machine_get_auto_kernel_cmdline,
|
|
microvm_machine_set_auto_kernel_cmdline);
|
|
object_class_property_set_description(oc,
|
|
MICROVM_MACHINE_AUTO_KERNEL_CMDLINE,
|
|
"Set off to disable adding virtio-mmio devices to the kernel cmdline");
|
|
|
|
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
|
|
}
|
|
|
|
static const TypeInfo microvm_machine_info = {
|
|
.name = TYPE_MICROVM_MACHINE,
|
|
.parent = TYPE_X86_MACHINE,
|
|
.instance_size = sizeof(MicrovmMachineState),
|
|
.instance_init = microvm_machine_initfn,
|
|
.class_size = sizeof(MicrovmMachineClass),
|
|
.class_init = microvm_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_HOTPLUG_HANDLER },
|
|
{ }
|
|
},
|
|
};
|
|
|
|
static void microvm_machine_init(void)
|
|
{
|
|
type_register_static(µvm_machine_info);
|
|
}
|
|
type_init(microvm_machine_init);
|