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qemu-e2k/target/riscv
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Bastian Koppelmann f2ab172867 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13 10:40:50 +01:00
..
insn_trans
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2019-03-13 10:40:50 +01:00
cpu_bits.h
RISC-V: Add misa runtime write support
2019-02-11 15:56:22 -08:00
cpu_helper.c
RISC-V: Use riscv prefix consistently on cpu helpers
2019-02-11 15:56:21 -08:00
cpu_user.h
RISC-V Linux User Emulation
2018-03-07 08:30:28 +13:00
cpu.c
RISC-V: Add misa runtime write support
2019-02-11 15:56:22 -08:00
cpu.h
RISC-V: Add misa runtime write support
2019-02-11 15:56:22 -08:00
csr.c
target/riscv: fix counter-enable checks in ctr()
2019-02-11 15:56:22 -08:00
fpu_helper.c
RISC-V: Use riscv prefix consistently on cpu helpers
2019-02-11 15:56:21 -08:00
gdbstub.c
RISC-V: Implement modular CSR helper interface
2019-01-08 13:59:09 -08:00
helper.h
RISC-V CPU Helpers
2018-03-07 08:30:28 +13:00
insn16.decode
target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2019-03-13 10:40:46 +01:00
insn32-64.decode
target/riscv: Convert RV64D insns to decodetree
2019-03-13 10:34:06 +01:00
insn32.decode
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2019-03-13 10:40:50 +01:00
instmap.h
RISC-V TCG Code Generation
2018-03-07 08:30:28 +13:00
Makefile.objs
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-13 10:34:06 +01:00
op_helper.c
RISC-V: Use riscv prefix consistently on cpu helpers
2019-02-11 15:56:21 -08:00
pmp.c
target/riscv/pmp.c: Fix pmp_decode_napot()
2018-12-20 12:26:39 -08:00
pmp.h
RISC-V Physical Memory Protection
2018-03-07 08:30:28 +13:00
translate.c
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2019-03-13 10:40:50 +01:00