Nikunj A Dadhania f34001ec96 target-ppc: improve lxvw4x implementation ... Load 8byte at a time and manipulate. Big-Endian Storage +-------------+-------------+-------------+-------------+ | 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF | +-------------+-------------+-------------+-------------+ Little-Endian Storage +-------------+-------------+-------------+-------------+ | 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC | +-------------+-------------+-------------+-------------+ Vector load results in (32-bit elements): +----------+----------+----------+----------+ | 00112233 | 44556677 | 8899AABB | CCDDEEFF | +----------+----------+----------+----------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Slight tweak to commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2016-10-05 11:05:28 +11:00
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dfp-impl.inc.c	ppc: Rename #include'd .c files to .inc.c	2016-09-07 12:40:12 +10:00
dfp-ops.inc.c	ppc: Rename #include'd .c files to .inc.c	2016-09-07 12:40:12 +10:00
fp-impl.inc.c	target-ppc: convert st64 to use new macro	2016-09-23 10:29:40 +10:00
fp-ops.inc.c	target-ppc: convert st64 to use new macro	2016-09-23 10:29:40 +10:00
spe-impl.inc.c	target-ppc: convert st64 to use new macro	2016-09-23 10:29:40 +10:00
spe-ops.inc.c	ppc: Rename #include'd .c files to .inc.c	2016-09-07 12:40:12 +10:00
vmx-impl.inc.c	target-ppc: convert st64 to use new macro	2016-09-23 10:29:40 +10:00
vmx-ops.inc.c	target-ppc: add vector permute right indexed instruction	2016-09-23 10:29:40 +10:00
vsx-impl.inc.c	target-ppc: improve lxvw4x implementation	2016-10-05 11:05:28 +11:00
vsx-ops.inc.c	target-ppc: Implement mtvsrdd instruction	2016-10-05 11:05:28 +11:00