343 lines
8.7 KiB
C
343 lines
8.7 KiB
C
/*
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* Sparc CPU init helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "helper-tcg.h"
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#include "qemu/module.h"
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#include "qemu/qemu-print.h"
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#include "exec/exec-all.h"
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#include "hw/qdev-properties.h"
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#include "qapi/visitor.h"
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#include "hw/core/tcg-cpu-ops.h"
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//#define DEBUG_FEATURES
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static void e2k_cpu_reset(DeviceState *dev)
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{
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CPUState *cs = CPU(dev);
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E2KCPU *cpu = E2K_CPU(cs);
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E2KCPUClass *ecc = E2K_CPU_GET_CLASS(cpu);
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CPUE2KState *env = &cpu->env;
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ecc->parent_reset(dev);
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memset(env, 0, offsetof(CPUE2KState, end_reset_fields));
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env->psr = PSR_PM;
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env->upsr = UPSR_NMIE | UPSR_FE;
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env->wd.base = 0;
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env->wd.size = 16;
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env->wd.psize = 8;
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env->bn.base = 8;
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env->bn.size = 8;
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env->bn.cur = 0;
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/* Based predicate window must not be zero. */
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env->bp.size = 1;
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env->aau.incrs[0] = 1; /* always one */
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env->fpcr._one = 1;
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env->fpcr.pc = FPCR_PC_XP;
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env->fpcr.em = FP_EM;
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env->pfpfr.em = FP_EM;
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e2k_update_fp_status(env);
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e2k_update_fx_status(env);
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// FIXME: testing
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env->idr = 0x3a207; /* mimic 8c */
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// FIXME: correct values
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env->psp.base = 0x810000;
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env->psp.size = 0x100000;
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env->pcsp.base = 0x910000;
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env->pcsp.size = 0xa10000;
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}
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#ifdef CONFIG_SOFTMMU
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static bool e2k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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qemu_log_mask(LOG_UNIMP, "e2k_cpu_exec_interrupt: not implemented\n");
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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e2k_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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#endif
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void e2k_cpu_do_interrupt(CPUState *cs)
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{
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qemu_log_mask(LOG_UNIMP, "e2k_cpu_do_interrupt: not implemented\n");
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cs->exception_index = -1;
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}
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static void cpu_e2k_disas_set_info(CPUState *cs, disassemble_info *info)
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{
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E2KCPU *cpu = E2K_CPU(cs);
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CPUE2KState *env = &cpu->env;
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info->mach = env->version * 3;
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info->print_insn = print_insn_e2k;
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}
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/* https://www.altlinux.org/Модели_процессоров_Эльбрус */
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#define DEFAULT_CPU_MODEL "e8c"
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static const struct e2k_def_t e2k_defs[] = {
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{
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.name = "e2c+", /* however it may work better */
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.canonical_name = "MCST Elbrus 2C+ (Monocube)",
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.gdb_arch = "elbrus-v2",
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.isa_version = 2,
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},
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{
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.name = "e2s",
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.canonical_name = "MCST Elbrus 4C",
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.gdb_arch = "elbrus-v3",
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.isa_version = 3,
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},
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{
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.name = "e8c", /* default choice for system */
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.canonical_name = "MCST Elbrus 8C",
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.gdb_arch = "elbrus-8c",
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.isa_version = 4,
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},
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{
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.name = "e8c2",
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.canonical_name = "MCST Elbrus 8CB",
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.gdb_arch = "elbrus-v5",
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.isa_version = 5,
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},
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{
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.name = "e16c",
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.canonical_name = "MCST Elbrus 16C",
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.gdb_arch = "elbrus-v6",
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.isa_version = 6,
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},
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};
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static void e2k_cpu_set_pc(CPUState *cs, vaddr value)
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{
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E2KCPU *cpu = E2K_CPU(cs);
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cpu->env.ip = value;
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}
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static void e2k_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
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{
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E2KCPU *cpu = E2K_CPU(cs);
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cpu->env.ip = tb->pc;
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}
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static bool e2k_cpu_has_work(CPUState *cs)
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{
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// TODO: e2k_cpu_has_work
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qemu_log_mask(LOG_UNIMP, "e2k_cpu_has_work: not implemented\n");
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return true;
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}
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static char *e2k_cpu_type_name(const char *cpu_model)
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{
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return g_strdup(cpu_model);
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}
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static ObjectClass *e2k_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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#ifdef CONFIG_USER_ONLY
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if (!strcasecmp(cpu_model, "any")) {
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cpu_model = DEFAULT_CPU_MODEL;
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}
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#endif
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typename = e2k_cpu_type_name(cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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return oc;
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}
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static void e2k_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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E2KCPUClass *ecc = E2K_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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E2KCPU *cpu = E2K_CPU(dev);
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CPUE2KState *env = &cpu->env;
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env->version = env->def.isa_version;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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e2k_cpu_register_gdb_regs_for_features(cs);
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qemu_init_vcpu(cs);
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ecc->parent_realize(dev, errp);
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}
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static void e2k_cpu_initfn(Object* obj)
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{
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E2KCPU *cpu = E2K_CPU(obj);
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E2KCPUClass *ecc = E2K_CPU_GET_CLASS(obj);
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CPUE2KState *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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if (ecc->cpu_def) {
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env->def = *ecc->cpu_def;
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}
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}
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static gchar* e2k_cpu_gdb_arch_name(CPUState *cs)
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{
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E2KCPU *cpu = E2K_CPU(cs);
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CPUE2KState *env = &cpu->env;
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return g_strdup_printf("%s:%d", env->def.gdb_arch, TARGET_LONG_BITS);
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}
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static struct TCGCPUOps e2k_tcg_ops = {
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.initialize = e2k_tcg_initialize,
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.synchronize_from_tb = e2k_cpu_synchronize_from_tb,
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.do_interrupt = e2k_cpu_do_interrupt,
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#ifdef CONFIG_SOFTMMU
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.cpu_exec_interrupt = e2k_cpu_exec_interrupt,
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.tlb_fill = e2k_cpu_tlb_fill,
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#endif
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};
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static Property e2k_cpu_properties[] = {
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DEFINE_PROP_BOOL("force_save_alc_dst", E2KCPU, env.force_save_alc_dst, false),
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DEFINE_PROP_BOOL("tags", E2KCPU, env.enable_tags, false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void e2k_cpu_class_init(ObjectClass *oc, void *data)
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{
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E2KCPUClass *ecc = E2K_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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device_class_set_parent_realize(dc, e2k_cpu_realizefn,
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&ecc->parent_realize);
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device_class_set_props(dc, e2k_cpu_properties);
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device_class_set_parent_reset(dc, e2k_cpu_reset, &ecc->parent_reset);
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cc->has_work = e2k_cpu_has_work;
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cc->dump_state = e2k_cpu_dump_state;
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cc->set_pc = e2k_cpu_set_pc;
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cc->class_by_name = e2k_cpu_class_by_name;
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cc->disas_set_info = cpu_e2k_disas_set_info;
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cc->gdb_core_xml_file = "e2k-v1.xml";
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cc->gdb_arch_name = e2k_cpu_gdb_arch_name;
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cc->gdb_read_register = e2k_cpu_gdb_read_register;
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cc->gdb_write_register = e2k_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 574;
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cc->tcg_ops = &e2k_tcg_ops;
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}
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static const TypeInfo e2k_cpu_type_info = {
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.name = TYPE_E2K_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(E2KCPU),
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.instance_init = e2k_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(E2KCPUClass),
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.class_init = e2k_cpu_class_init,
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};
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static void e2k_cpu_cpudef_class_init(ObjectClass *oc, void *data)
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{
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E2KCPUClass *ecc = E2K_CPU_CLASS(oc);
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ecc->cpu_def = data;
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}
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static void e2k_register_cpudef_type(const struct e2k_def_t *def)
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{
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char *typename = e2k_cpu_type_name(def->name);
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TypeInfo ti = {
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.name = typename,
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.parent = TYPE_E2K_CPU,
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.class_init = e2k_cpu_cpudef_class_init,
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.class_data = (void *)def,
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};
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type_register(&ti);
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g_free(typename);
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}
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static void e2k_cpu_register_types(void)
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{
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int i;
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type_register_static(&e2k_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(e2k_defs); i++) {
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e2k_register_cpudef_type(&e2k_defs[i]);
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}
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}
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type_init(e2k_cpu_register_types)
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void e2k_cpu_list(void)
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{
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unsigned int i;
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Property* prop;
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size_t len = 0;
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for (i = 0; i < ARRAY_SIZE(e2k_defs); i++) {
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qemu_printf("%6s (%-30s) ISA version: v%d\n",
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e2k_defs[i].name,
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e2k_defs[i].canonical_name,
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e2k_defs[i].isa_version
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);
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}
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qemu_printf("\nFeatures:\n");
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for (prop = e2k_cpu_properties; prop->name != 0; prop++) {
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size_t l = strlen(prop->name) + 1;
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if (len + l >= 75) {
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qemu_printf("\n");
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len = 0;
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}
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qemu_printf("%s%s", len ? " " : " ", prop->name);
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len += l;
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}
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qemu_printf("\n");
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}
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void e2k_psp_new(E2KPsp *psp, uint32_t size, uint64_t base, uint64_t base_tags)
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{
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psp->is_readable = true;
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psp->is_writable = true;
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psp->index = 0;
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psp->size = size;
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psp->base = base;
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psp->base_tag = base_tags;
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}
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