qemu-e2k/linux-user/riscv
Richard Henderson e91a7227cb target/riscv: Split misa.mxl and misa.ext
The hw representation of misa.mxl is at the high bits of the
misa csr.  Representing this in the same way inside QEMU
results in overly complex code trying to check that field.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22 07:47:51 +10:00
..
cpu_loop.c target/riscv: Split misa.mxl and misa.ext 2021-10-22 07:47:51 +10:00
signal.c linux-user/riscv: Implement setup_sigtramp 2021-10-01 12:03:48 +02:00
sockbits.h linux-user: move socket.h generic definitions to generic/sockbits.h 2018-05-25 10:10:55 +02:00
syscall32_nr.h linux-user: update syscall_nr.h to Linux v5.13 2021-07-13 13:59:59 +02:00
syscall64_nr.h linux-user: update syscall_nr.h to Linux v5.13 2021-07-13 13:59:59 +02:00
syscall_nr.h linux-user/riscv: Update the syscall_nr's to the 5.5 kernel 2020-03-20 16:01:59 +01:00
target_cpu.h linux-user: Introduce cpu_clone_regs_parent 2019-11-06 13:43:25 +01:00
target_elf.h linux-user/riscv: Add the CPU type as a comment 2019-05-24 12:09:23 -07:00
target_errno_defs.h linux-user: Extract target errno to 'target_errno_defs.h' 2021-07-12 21:53:35 +02:00
target_fcntl.h linux-user: move generic fcntl definitions to generic/fcntl.h 2018-06-04 01:30:43 +02:00
target_signal.h linux-user/riscv: Implement setup_sigtramp 2021-10-01 12:03:48 +02:00
target_structs.h linux-user/nios2 linux-user/riscv: Clean up header guards 2019-05-13 08:58:55 +02:00
target_syscall.h linux-user: Add strace support for printing arguments of syscalls used to lock and unlock memory 2020-08-27 12:29:50 +02:00
termbits.h linux-user: Add generic 'termbits.h' for some archs 2020-08-27 12:29:50 +02:00