f502cfc207
Implement handling for the AArch64 SP_EL0 system register. This holds the EL0 stack pointer, and is only accessible when it's not being used as the stack pointer, ie when we're in EL1 and EL1 is using its own stack pointer. We also provide a definition of the SP_EL1 register; this isn't guest visible as a system register for an implementation like QEMU which doesn't provide EL2 or EL3; however it is useful for ensuring the underlying state is migrated. We need to update the state fields in the CPU state whenever we switch stack pointers; this happens when we take an exception and also when SPSEL is used to change the bit in PSTATE which indicates which stack pointer EL1 should use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
249 lines
6.4 KiB
C
249 lines
6.4 KiB
C
/*
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* ARM implementation of KVM hooks, 64 bit specific code
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*
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* Copyright Mian-M. Hamayun 2013, Virtual Open Systems
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <stdio.h>
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "cpu.h"
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#include "hw/arm/arm.h"
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static inline void set_feature(uint64_t *features, int feature)
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{
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*features |= 1ULL << feature;
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}
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bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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* For AArch64 we currently don't care about ID registers at
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* all; we just want to know the CPU type.
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*/
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int fdarray[3];
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uint64_t features = 0;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type. Fortunately these old kernels
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* support only a very limited number of CPUs.
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*/
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static const uint32_t cpus_to_try[] = {
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KVM_ARM_TARGET_AEM_V8,
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KVM_ARM_TARGET_FOUNDATION_V8,
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KVM_ARM_TARGET_CORTEX_A57,
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QEMU_KVM_ARM_TARGET_NONE
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};
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struct kvm_vcpu_init init;
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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ahcc->target = init.target;
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ahcc->dtb_compatible = "arm,arm-v8";
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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/* We can assume any KVM supporting CPU is at least a v8
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* with VFPv4+Neon; this in turn implies most of the other
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* feature bits.
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*/
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set_feature(&features, ARM_FEATURE_V8);
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set_feature(&features, ARM_FEATURE_VFP4);
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set_feature(&features, ARM_FEATURE_NEON);
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set_feature(&features, ARM_FEATURE_AARCH64);
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ahcc->features = features;
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return true;
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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struct kvm_vcpu_init init;
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int ret;
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
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!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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fprintf(stderr, "KVM is not supported for this guest CPU type\n");
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return -EINVAL;
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}
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init.target = cpu->kvm_target;
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memset(init.features, 0, sizeof(init.features));
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if (cpu->start_powered_off) {
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init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
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}
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ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
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/* TODO : support for save/restore/reset of system regs via tuple list */
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return ret;
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}
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#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
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int kvm_arch_put_registers(CPUState *cs, int level)
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{
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struct kvm_one_reg reg;
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uint64_t val;
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int i;
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int ret;
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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for (i = 0; i < 31; i++) {
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reg.id = AARCH64_CORE_REG(regs.regs[i]);
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reg.addr = (uintptr_t) &env->xregs[i];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
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* QEMU side we keep the current SP in xregs[31] as well.
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*/
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if (env->pstate & PSTATE_SP) {
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env->sp_el[1] = env->xregs[31];
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} else {
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env->sp_el[0] = env->xregs[31];
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}
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reg.id = AARCH64_CORE_REG(regs.sp);
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reg.addr = (uintptr_t) &env->sp_el[0];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(sp_el1);
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reg.addr = (uintptr_t) &env->sp_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
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val = pstate_read(env);
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reg.id = AARCH64_CORE_REG(regs.pstate);
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reg.addr = (uintptr_t) &val;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(regs.pc);
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reg.addr = (uintptr_t) &env->pc;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(elr_el1);
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reg.addr = (uintptr_t) &env->elr_el1;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* TODO:
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* SPSR[]
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* FP state
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* system registers
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*/
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return ret;
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}
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int kvm_arch_get_registers(CPUState *cs)
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{
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struct kvm_one_reg reg;
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uint64_t val;
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int i;
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int ret;
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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for (i = 0; i < 31; i++) {
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reg.id = AARCH64_CORE_REG(regs.regs[i]);
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reg.addr = (uintptr_t) &env->xregs[i];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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reg.id = AARCH64_CORE_REG(regs.sp);
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reg.addr = (uintptr_t) &env->sp_el[0];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(sp_el1);
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reg.addr = (uintptr_t) &env->sp_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(regs.pstate);
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reg.addr = (uintptr_t) &val;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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pstate_write(env, val);
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/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
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* QEMU side we keep the current SP in xregs[31] as well.
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*/
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if (env->pstate & PSTATE_SP) {
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env->xregs[31] = env->sp_el[1];
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} else {
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env->xregs[31] = env->sp_el[0];
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}
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reg.id = AARCH64_CORE_REG(regs.pc);
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reg.addr = (uintptr_t) &env->pc;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(elr_el1);
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reg.addr = (uintptr_t) &env->elr_el1;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* TODO: other registers */
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return ret;
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}
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void kvm_arch_reset_vcpu(CPUState *cs)
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{
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}
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