1f5c00cfdb
It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
328 lines
8.2 KiB
C
328 lines
8.2 KiB
C
/*
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* QEMU LatticeMico32 CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "exec/exec-all.h"
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static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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cpu->env.pc = value;
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}
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/* Sort alphabetically by type name. */
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static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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return strcmp(name_a, name_b);
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}
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static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CPUListState *s = user_data;
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const char *typename = object_class_get_name(oc);
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char *name;
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
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(*s->cpu_fprintf)(s->file, " %s\n", name);
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g_free(name);
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}
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void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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CPUListState s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_LM32_CPU, false);
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list = g_slist_sort(list, lm32_cpu_list_compare);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, lm32_cpu_list_entry, &s);
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g_slist_free(list);
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}
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static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
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{
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CPULM32State *env = &cpu->env;
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uint32_t cfg = 0;
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if (cpu->features & LM32_FEATURE_MULTIPLY) {
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cfg |= CFG_M;
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}
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if (cpu->features & LM32_FEATURE_DIVIDE) {
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cfg |= CFG_D;
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}
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if (cpu->features & LM32_FEATURE_SHIFT) {
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cfg |= CFG_S;
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}
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if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
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cfg |= CFG_X;
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}
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if (cpu->features & LM32_FEATURE_I_CACHE) {
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cfg |= CFG_IC;
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}
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if (cpu->features & LM32_FEATURE_D_CACHE) {
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cfg |= CFG_DC;
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}
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if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
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cfg |= CFG_CC;
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}
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cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
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cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
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cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
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cfg |= (cpu->revision << CFG_REV_SHIFT);
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env->cfg = cfg;
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}
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static bool lm32_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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/* CPUClass::reset() */
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static void lm32_cpu_reset(CPUState *s)
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{
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LM32CPU *cpu = LM32_CPU(s);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
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CPULM32State *env = &cpu->env;
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lcc->parent_reset(s);
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/* reset cpu state */
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memset(env, 0, offsetof(CPULM32State, end_reset_fields));
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lm32_cpu_init_cfg_reg(cpu);
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}
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static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_lm32;
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info->print_insn = print_insn_lm32;
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}
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static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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lcc->parent_realize(dev, errp);
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}
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static void lm32_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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LM32CPU *cpu = LM32_CPU(obj);
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CPULM32State *env = &cpu->env;
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static bool tcg_initialized;
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cs->env_ptr = env;
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env->flags = 0;
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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lm32_translate_init();
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}
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}
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static void lm32_basic_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_standard_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_full_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_D_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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typedef struct LM32CPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} LM32CPUInfo;
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static const LM32CPUInfo lm32_cpus[] = {
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{
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.name = "lm32-basic",
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.initfn = lm32_basic_cpu_initfn,
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},
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{
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.name = "lm32-standard",
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.initfn = lm32_standard_cpu_initfn,
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},
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{
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.name = "lm32-full",
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.initfn = lm32_full_cpu_initfn,
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},
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};
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static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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if (cpu_model == NULL) {
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return NULL;
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}
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typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
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object_class_is_abstract(oc))) {
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oc = NULL;
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}
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return oc;
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}
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static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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{
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LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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lcc->parent_realize = dc->realize;
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dc->realize = lm32_cpu_realizefn;
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lcc->parent_reset = cc->reset;
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cc->reset = lm32_cpu_reset;
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cc->class_by_name = lm32_cpu_class_by_name;
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cc->has_work = lm32_cpu_has_work;
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cc->do_interrupt = lm32_cpu_do_interrupt;
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cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
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cc->dump_state = lm32_cpu_dump_state;
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cc->set_pc = lm32_cpu_set_pc;
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cc->gdb_read_register = lm32_cpu_gdb_read_register;
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cc->gdb_write_register = lm32_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_lm32_cpu;
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#endif
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cc->gdb_num_core_regs = 32 + 7;
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cc->gdb_stop_before_watchpoint = true;
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cc->debug_excp_handler = lm32_debug_excp_handler;
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cc->disas_set_info = lm32_cpu_disas_set_info;
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}
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static void lm32_register_cpu_type(const LM32CPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_LM32_CPU,
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.instance_init = info->initfn,
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};
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type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo lm32_cpu_type_info = {
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.name = TYPE_LM32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(LM32CPU),
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.instance_init = lm32_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(LM32CPUClass),
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.class_init = lm32_cpu_class_init,
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};
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static void lm32_cpu_register_types(void)
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{
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int i;
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type_register_static(&lm32_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
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lm32_register_cpu_type(&lm32_cpus[i]);
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}
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}
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type_init(lm32_cpu_register_types)
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