qemu-e2k

History

Richard Henderson b1669e5e32 target: Include softmmu_exec.h where forgotten Several targets forgot to include softmmu_exec.h, which would break them with a header cleanup to follow. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>		2013-09-02 09:08:30 -07:00
..
cpu-qom.h	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
cpu.c	cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"	2013-07-29 15:29:15 +02:00
cpu.h	cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()	2013-07-23 02:41:32 +02:00
gdbstub.c	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
helper.c	cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook	2013-07-23 02:41:33 +02:00
helper.h
machine.c
Makefile.objs	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
op_helper.c	target: Include softmmu_exec.h where forgotten	2013-09-02 09:08:30 -07:00
README
TODO
translate.c	tcg: Change tcg_gen_exit_tb argument to uintptr_t	2013-09-02 09:08:30 -07:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);