f720f20350
Create a custom address space for PCI memory region and use it for the PCI bus. Dynamically handle PCI0 Mem0 and PCI0 Mem1 regions, as already done for PCI0 IO. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>