2914fc61d5
They're actually more commonly used than the helper without _under_bus, because most callers do have the pci bus on hand. After exporting we can switch a lot of the call sites to use these two helpers. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20211028043129.38871-3-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au>
446 lines
15 KiB
C
446 lines
15 KiB
C
/*
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* QEMU sPAPR PCI for NVLink2 pass through
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*
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* Copyright (c) 2019 Alexey Kardashevskiy, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-host/spapr.h"
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#include "hw/ppc/spapr_numa.h"
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#include "qemu/error-report.h"
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#include "hw/ppc/fdt.h"
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#include "hw/pci/pci_bridge.h"
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#define PHANDLE_PCIDEV(phb, pdev) (0x12000000 | \
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(((phb)->index) << 16) | ((pdev)->devfn))
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#define PHANDLE_GPURAM(phb, n) (0x110000FF | ((n) << 8) | \
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(((phb)->index) << 16))
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#define PHANDLE_NVLINK(phb, gn, nn) (0x00130000 | (((phb)->index) << 8) | \
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((gn) << 4) | (nn))
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typedef struct SpaprPhbPciNvGpuSlot {
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uint64_t tgt;
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uint64_t gpa;
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unsigned numa_id;
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PCIDevice *gpdev;
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int linknum;
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struct {
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uint64_t atsd_gpa;
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PCIDevice *npdev;
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uint32_t link_speed;
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} links[NVGPU_MAX_LINKS];
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} SpaprPhbPciNvGpuSlot;
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struct SpaprPhbPciNvGpuConfig {
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uint64_t nv2_ram_current;
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uint64_t nv2_atsd_current;
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int num; /* number of non empty (i.e. tgt!=0) entries in slots[] */
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SpaprPhbPciNvGpuSlot slots[NVGPU_MAX_NUM];
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Error *err;
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};
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static SpaprPhbPciNvGpuSlot *
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spapr_nvgpu_get_slot(SpaprPhbPciNvGpuConfig *nvgpus, uint64_t tgt)
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{
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int i;
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/* Search for partially collected "slot" */
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for (i = 0; i < nvgpus->num; ++i) {
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if (nvgpus->slots[i].tgt == tgt) {
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return &nvgpus->slots[i];
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}
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}
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if (nvgpus->num == ARRAY_SIZE(nvgpus->slots)) {
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return NULL;
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}
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i = nvgpus->num;
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nvgpus->slots[i].tgt = tgt;
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++nvgpus->num;
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return &nvgpus->slots[i];
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}
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static void spapr_pci_collect_nvgpu(SpaprPhbPciNvGpuConfig *nvgpus,
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PCIDevice *pdev, uint64_t tgt,
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MemoryRegion *mr, Error **errp)
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{
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MachineState *machine = MACHINE(qdev_get_machine());
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SpaprMachineState *spapr = SPAPR_MACHINE(machine);
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SpaprPhbPciNvGpuSlot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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if (!nvslot) {
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error_setg(errp, "Found too many GPUs per vPHB");
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return;
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}
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g_assert(!nvslot->gpdev);
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nvslot->gpdev = pdev;
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nvslot->gpa = nvgpus->nv2_ram_current;
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nvgpus->nv2_ram_current += memory_region_size(mr);
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nvslot->numa_id = spapr->gpu_numa_id;
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++spapr->gpu_numa_id;
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}
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static void spapr_pci_collect_nvnpu(SpaprPhbPciNvGpuConfig *nvgpus,
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PCIDevice *pdev, uint64_t tgt,
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MemoryRegion *mr, Error **errp)
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{
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SpaprPhbPciNvGpuSlot *nvslot = spapr_nvgpu_get_slot(nvgpus, tgt);
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int j;
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if (!nvslot) {
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error_setg(errp, "Found too many NVLink bridges per vPHB");
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return;
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}
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j = nvslot->linknum;
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if (j == ARRAY_SIZE(nvslot->links)) {
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error_setg(errp, "Found too many NVLink bridges per GPU");
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return;
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}
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++nvslot->linknum;
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g_assert(!nvslot->links[j].npdev);
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nvslot->links[j].npdev = pdev;
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nvslot->links[j].atsd_gpa = nvgpus->nv2_atsd_current;
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nvgpus->nv2_atsd_current += memory_region_size(mr);
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nvslot->links[j].link_speed =
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object_property_get_uint(OBJECT(pdev), "nvlink2-link-speed", NULL);
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}
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static void spapr_phb_pci_collect_nvgpu(PCIBus *bus, PCIDevice *pdev,
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void *opaque)
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{
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PCIBus *sec_bus;
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Object *po = OBJECT(pdev);
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uint64_t tgt = object_property_get_uint(po, "nvlink2-tgt", NULL);
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if (tgt) {
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Error *local_err = NULL;
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SpaprPhbPciNvGpuConfig *nvgpus = opaque;
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Object *mr_gpu = object_property_get_link(po, "nvlink2-mr[0]", NULL);
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Object *mr_npu = object_property_get_link(po, "nvlink2-atsd-mr[0]",
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NULL);
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g_assert(mr_gpu || mr_npu);
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if (mr_gpu) {
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spapr_pci_collect_nvgpu(nvgpus, pdev, tgt, MEMORY_REGION(mr_gpu),
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&local_err);
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} else {
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spapr_pci_collect_nvnpu(nvgpus, pdev, tgt, MEMORY_REGION(mr_npu),
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&local_err);
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}
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error_propagate(&nvgpus->err, local_err);
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}
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if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
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PCI_HEADER_TYPE_BRIDGE)) {
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return;
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}
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sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
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if (!sec_bus) {
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return;
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}
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pci_for_each_device_under_bus(sec_bus, spapr_phb_pci_collect_nvgpu, opaque);
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}
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void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
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{
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int i, j, valid_gpu_num;
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PCIBus *bus;
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/* Search for GPUs and NPUs */
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if (!sphb->nv2_gpa_win_addr || !sphb->nv2_atsd_win_addr) {
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return;
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}
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sphb->nvgpus = g_new0(SpaprPhbPciNvGpuConfig, 1);
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sphb->nvgpus->nv2_ram_current = sphb->nv2_gpa_win_addr;
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sphb->nvgpus->nv2_atsd_current = sphb->nv2_atsd_win_addr;
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bus = PCI_HOST_BRIDGE(sphb)->bus;
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pci_for_each_device_under_bus(bus, spapr_phb_pci_collect_nvgpu,
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sphb->nvgpus);
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if (sphb->nvgpus->err) {
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error_propagate(errp, sphb->nvgpus->err);
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sphb->nvgpus->err = NULL;
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goto cleanup_exit;
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}
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/* Add found GPU RAM and ATSD MRs if found */
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for (i = 0, valid_gpu_num = 0; i < sphb->nvgpus->num; ++i) {
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Object *nvmrobj;
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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if (!nvslot->gpdev) {
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continue;
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}
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nvmrobj = object_property_get_link(OBJECT(nvslot->gpdev),
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"nvlink2-mr[0]", NULL);
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/* ATSD is pointless without GPU RAM MR so skip those */
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if (!nvmrobj) {
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continue;
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}
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++valid_gpu_num;
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memory_region_add_subregion(get_system_memory(), nvslot->gpa,
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MEMORY_REGION(nvmrobj));
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for (j = 0; j < nvslot->linknum; ++j) {
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Object *atsdmrobj;
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atsdmrobj = object_property_get_link(OBJECT(nvslot->links[j].npdev),
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"nvlink2-atsd-mr[0]", NULL);
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if (!atsdmrobj) {
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continue;
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}
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memory_region_add_subregion(get_system_memory(),
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nvslot->links[j].atsd_gpa,
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MEMORY_REGION(atsdmrobj));
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}
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}
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if (valid_gpu_num) {
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return;
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}
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/* We did not find any interesting GPU */
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cleanup_exit:
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g_free(sphb->nvgpus);
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sphb->nvgpus = NULL;
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}
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void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
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{
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int i, j;
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if (!sphb->nvgpus) {
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return;
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}
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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Object *nv_mrobj = object_property_get_link(OBJECT(nvslot->gpdev),
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"nvlink2-mr[0]", NULL);
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if (nv_mrobj) {
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memory_region_del_subregion(get_system_memory(),
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MEMORY_REGION(nv_mrobj));
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}
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for (j = 0; j < nvslot->linknum; ++j) {
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PCIDevice *npdev = nvslot->links[j].npdev;
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Object *atsd_mrobj;
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atsd_mrobj = object_property_get_link(OBJECT(npdev),
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"nvlink2-atsd-mr[0]", NULL);
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if (atsd_mrobj) {
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memory_region_del_subregion(get_system_memory(),
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MEMORY_REGION(atsd_mrobj));
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}
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}
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}
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g_free(sphb->nvgpus);
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sphb->nvgpus = NULL;
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}
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void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
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Error **errp)
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{
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int i, j, atsdnum = 0;
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uint64_t atsd[8]; /* The existing limitation of known guests */
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if (!sphb->nvgpus) {
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return;
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}
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for (i = 0; (i < sphb->nvgpus->num) && (atsdnum < ARRAY_SIZE(atsd)); ++i) {
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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if (!nvslot->gpdev) {
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continue;
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}
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for (j = 0; j < nvslot->linknum; ++j) {
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if (!nvslot->links[j].atsd_gpa) {
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continue;
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}
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if (atsdnum == ARRAY_SIZE(atsd)) {
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error_report("Only %"PRIuPTR" ATSD registers supported",
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ARRAY_SIZE(atsd));
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break;
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}
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atsd[atsdnum] = cpu_to_be64(nvslot->links[j].atsd_gpa);
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++atsdnum;
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}
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}
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if (!atsdnum) {
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error_setg(errp, "No ATSD registers found");
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return;
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}
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if (!spapr_phb_eeh_available(sphb)) {
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/*
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* ibm,mmio-atsd contains ATSD registers; these belong to an NPU PHB
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* which we do not emulate as a separate device. Instead we put
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* ibm,mmio-atsd to the vPHB with GPU and make sure that we do not
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* put GPUs from different IOMMU groups to the same vPHB to ensure
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* that the guest will use ATSDs from the corresponding NPU.
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*/
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error_setg(errp, "ATSD requires separate vPHB per GPU IOMMU group");
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return;
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}
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_FDT((fdt_setprop(fdt, bus_off, "ibm,mmio-atsd", atsd,
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atsdnum * sizeof(atsd[0]))));
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}
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void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
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{
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int i, j, linkidx, npuoff;
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char *npuname;
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if (!sphb->nvgpus) {
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return;
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}
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npuname = g_strdup_printf("npuphb%d", sphb->index);
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npuoff = fdt_add_subnode(fdt, 0, npuname);
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_FDT(npuoff);
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_FDT(fdt_setprop_cell(fdt, npuoff, "#address-cells", 1));
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_FDT(fdt_setprop_cell(fdt, npuoff, "#size-cells", 0));
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/* Advertise NPU as POWER9 so the guest can enable NPU2 contexts */
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_FDT((fdt_setprop_string(fdt, npuoff, "compatible", "ibm,power9-npu")));
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g_free(npuname);
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for (i = 0, linkidx = 0; i < sphb->nvgpus->num; ++i) {
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for (j = 0; j < sphb->nvgpus->slots[i].linknum; ++j) {
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char *linkname = g_strdup_printf("link@%d", linkidx);
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int off = fdt_add_subnode(fdt, npuoff, linkname);
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_FDT(off);
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/* _FDT((fdt_setprop_cell(fdt, off, "reg", linkidx))); */
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_FDT((fdt_setprop_string(fdt, off, "compatible",
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"ibm,npu-link")));
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_FDT((fdt_setprop_cell(fdt, off, "phandle",
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PHANDLE_NVLINK(sphb, i, j))));
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_FDT((fdt_setprop_cell(fdt, off, "ibm,npu-link-index", linkidx)));
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g_free(linkname);
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++linkidx;
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}
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}
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/* Add memory nodes for GPU RAM and mark them unusable */
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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Object *nv_mrobj = object_property_get_link(OBJECT(nvslot->gpdev),
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"nvlink2-mr[0]",
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&error_abort);
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uint64_t size = object_property_get_uint(nv_mrobj, "size", NULL);
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uint64_t mem_reg[2] = { cpu_to_be64(nvslot->gpa), cpu_to_be64(size) };
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char *mem_name = g_strdup_printf("memory@%"PRIx64, nvslot->gpa);
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int off = fdt_add_subnode(fdt, 0, mem_name);
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_FDT(off);
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_FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
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_FDT((fdt_setprop(fdt, off, "reg", mem_reg, sizeof(mem_reg))));
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spapr_numa_write_associativity_dt(SPAPR_MACHINE(qdev_get_machine()),
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fdt, off, nvslot->numa_id);
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_FDT((fdt_setprop_string(fdt, off, "compatible",
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"ibm,coherent-device-memory")));
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mem_reg[1] = cpu_to_be64(0);
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_FDT((fdt_setprop(fdt, off, "linux,usable-memory", mem_reg,
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sizeof(mem_reg))));
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_FDT((fdt_setprop_cell(fdt, off, "phandle",
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PHANDLE_GPURAM(sphb, i))));
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g_free(mem_name);
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}
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}
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void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
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SpaprPhbState *sphb)
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{
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int i, j;
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if (!sphb->nvgpus) {
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return;
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}
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for (i = 0; i < sphb->nvgpus->num; ++i) {
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SpaprPhbPciNvGpuSlot *nvslot = &sphb->nvgpus->slots[i];
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/* Skip "slot" without attached GPU */
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if (!nvslot->gpdev) {
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continue;
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}
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if (dev == nvslot->gpdev) {
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uint32_t npus[nvslot->linknum];
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for (j = 0; j < nvslot->linknum; ++j) {
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PCIDevice *npdev = nvslot->links[j].npdev;
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npus[j] = cpu_to_be32(PHANDLE_PCIDEV(sphb, npdev));
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}
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_FDT(fdt_setprop(fdt, offset, "ibm,npu", npus,
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j * sizeof(npus[0])));
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_FDT((fdt_setprop_cell(fdt, offset, "phandle",
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PHANDLE_PCIDEV(sphb, dev))));
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continue;
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}
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for (j = 0; j < nvslot->linknum; ++j) {
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if (dev != nvslot->links[j].npdev) {
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continue;
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}
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_FDT((fdt_setprop_cell(fdt, offset, "phandle",
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PHANDLE_PCIDEV(sphb, dev))));
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_FDT(fdt_setprop_cell(fdt, offset, "ibm,gpu",
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PHANDLE_PCIDEV(sphb, nvslot->gpdev)));
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_FDT((fdt_setprop_cell(fdt, offset, "ibm,nvlink",
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PHANDLE_NVLINK(sphb, i, j))));
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/*
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* If we ever want to emulate GPU RAM at the same location as on
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* the host - here is the encoding GPA->TGT:
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*
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* gta = ((sphb->nv2_gpa >> 42) & 0x1) << 42;
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* gta |= ((sphb->nv2_gpa >> 45) & 0x3) << 43;
|
|
* gta |= ((sphb->nv2_gpa >> 49) & 0x3) << 45;
|
|
* gta |= sphb->nv2_gpa & ((1UL << 43) - 1);
|
|
*/
|
|
_FDT(fdt_setprop_cell(fdt, offset, "memory-region",
|
|
PHANDLE_GPURAM(sphb, i)));
|
|
_FDT(fdt_setprop_u64(fdt, offset, "ibm,device-tgt-addr",
|
|
nvslot->tgt));
|
|
_FDT(fdt_setprop_cell(fdt, offset, "ibm,nvlink-speed",
|
|
nvslot->links[j].link_speed));
|
|
}
|
|
}
|
|
}
|