f85504b23a
This adds a simplistic emulation of the Sun GEM ethernet controller found in Apple ASICs. Currently we only support the Apple UniNorth 1.x variant, but the other Apple or Sun variants should mostly be a matter of adding PCI IDs options. We have a very primitive emulation of a single Broadcom 5201 PHY which is supported by the MacOS driver. This model brings out-of-the-box networking to MacOS 9, and all versions of OS X I tried with the mac99 platform. Further improvements from Mark: - Remove sungem.h file, moving constants into sungem.c as required - Switch to using tracepoints for debugging - Split register blocks into separate memory regions - Use arrays in SunGEMState to hold register values - Add state-saving support Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
325 lines
24 KiB
Plaintext
325 lines
24 KiB
Plaintext
# See docs/devel/tracing.txt for syntax documentation.
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# hw/net/lance.c
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lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
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lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
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# hw/net/milkymist-minimac2.c
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milkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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milkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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milkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr 0x%02x addr 0x%02x value 0x%04x"
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milkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr 0x%02x addr 0x%02x value 0x%04x"
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milkymist_minimac2_tx_frame(uint32_t length) "length %u"
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milkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u"
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milkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d"
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milkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX"
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milkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX"
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milkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX"
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# hw/net/mipsnet.c
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mipsnet_send(uint32_t size) "sending len=%u"
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mipsnet_receive(uint32_t size) "receiving len=%u"
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mipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x"
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mipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64
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mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (0x%02x)"
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# hw/net/opencores_eth.c
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open_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x"
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open_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x"
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open_eth_update_irq(uint32_t v) "IRQ <- 0x%x"
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open_eth_receive(unsigned len) "RX: len: %u"
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open_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x"
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open_eth_receive_reject(void) "RX: rejected"
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open_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x"
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open_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: 0x%08x, len: %u, tx_len: %u"
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open_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x"
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open_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x"
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open_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x"
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open_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x"
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# hw/net/pcnet.c
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pcnet_s_reset(void *s) "s=%p"
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pcnet_user_int(void *s) "s=%p"
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pcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old) "s=%p INTA=%d<=%d"
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pcnet_init(void *s, uint64_t init_addr) "s=%p init_addr=0x%"PRIx64
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pcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen) "s=%p rlen=%d tlen=%d"
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pcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl) "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]"
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# hw/net/pcnet-pci.c
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pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
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pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
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pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
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pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d"
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pcnet_mmio_writeb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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pcnet_mmio_writew(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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pcnet_mmio_writel(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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pcnet_mmio_readb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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pcnet_mmio_readw(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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pcnet_mmio_readl(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
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# hw/net/net_rx_pkt.c
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net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
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net_rx_pkt_l4_csum_validate_entry(void) "Starting L4 checksum validation"
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net_rx_pkt_l4_csum_validate_not_xxp(void) "Not a TCP/UDP packet"
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net_rx_pkt_l4_csum_validate_udp_with_no_checksum(void) "UDP packet without checksum"
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net_rx_pkt_l4_csum_validate_ip4_fragment(void) "IP4 fragment"
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net_rx_pkt_l4_csum_validate_csum(bool csum_valid) "Checksum valid: %d"
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net_rx_pkt_l4_csum_calc_entry(void) "Starting L4 checksum calculation"
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net_rx_pkt_l4_csum_calc_ip4_udp(void) "IP4/UDP packet"
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net_rx_pkt_l4_csum_calc_ip4_tcp(void) "IP4/TCP packet"
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net_rx_pkt_l4_csum_calc_ip6_udp(void) "IP6/UDP packet"
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net_rx_pkt_l4_csum_calc_ip6_tcp(void) "IP6/TCP packet"
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net_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, length %u"
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net_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum) "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X"
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net_rx_pkt_l4_csum_fix_entry(void) "Starting L4 checksum correction"
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net_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso) "TCP packet, L4 cso: %u"
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net_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso) "UDP packet, L4 cso: %u"
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net_rx_pkt_l4_csum_fix_not_xxp(void) "Not an IP4 packet"
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net_rx_pkt_l4_csum_fix_ip4_fragment(void) "IP4 fragment"
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net_rx_pkt_l4_csum_fix_udp_with_no_checksum(void) "UDP packet without checksum"
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net_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum) "L4 Checksum: Offset: %u, value 0x%X"
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net_rx_pkt_l3_csum_validate_entry(void) "Starting L3 checksum validation"
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net_rx_pkt_l3_csum_validate_not_ip4(void) "Not an IP4 packet"
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net_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid) "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d"
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net_rx_pkt_rss_ip4(void) "Calculating IPv4 RSS hash"
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net_rx_pkt_rss_ip4_tcp(void) "Calculating IPv4/TCP RSS hash"
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net_rx_pkt_rss_ip6_tcp(void) "Calculating IPv6/TCP RSS hash"
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net_rx_pkt_rss_ip6(void) "Calculating IPv6 RSS hash"
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net_rx_pkt_rss_ip6_ex(void) "Calculating IPv6/EX RSS hash"
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net_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash) "RSS hash for %zu bytes: 0x%X"
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net_rx_pkt_rss_add_chunk(void* ptr, size_t size, size_t input_offset) "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes"
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# hw/net/e1000x_common.c
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e1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master) "link_up: %d, rx_enabled %d, pci_master %d"
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e1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet) "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X"
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e1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x"
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e1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x"
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e1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val) "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x"
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e1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS = %u"
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e1000x_rx_disabled(uint32_t rctl_reg) "Received packet dropped because receive is disabled RCTL = %u"
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e1000x_rx_oversized(size_t size) "Received packet dropped because it was oversized (%zu bytes)"
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e1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x"
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e1000x_link_negotiation_start(void) "Start link auto negotiation"
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e1000x_link_negotiation_done(void) "Auto negotiation is completed"
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# hw/net/e1000e_core.c
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e1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
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e1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
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e1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x"
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e1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED"
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e1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x"
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e1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED"
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e1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X"
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e1000e_core_ctrl_sw_reset(void) "Doing SW reset"
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e1000e_core_ctrl_phy_reset(void) "Doing PHY reset"
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e1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d"
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e1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d"
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e1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d"
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e1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d"
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e1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d"
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e1000e_link_status_changed(bool status) "New link status: %d"
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e1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
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e1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64
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e1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)"
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e1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented."
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e1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented."
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e1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported"
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e1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported"
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e1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported"
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e1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported"
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e1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported"
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e1000e_tx_disabled(void) "TX Disabled"
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e1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x"
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e1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u"
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e1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full"
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e1000e_rx_can_recv(void) "Can receive"
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e1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u"
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e1000e_rx_null_descriptor(void) "Null RX descriptor!!"
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e1000e_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X"
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e1000e_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X"
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e1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]"
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e1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]"
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e1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]"
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e1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u"
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e1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
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e1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u"
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e1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x"
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e1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments"
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e1000e_rx_flt_dropped(void) "Received packet dropped by RX filter"
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e1000e_rx_written_to_guest(uint32_t causes) "Received packet written to guest (ICR causes %u)"
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e1000e_rx_not_written_to_guest(uint32_t causes) "Received packet NOT written to guest (ICR causes %u)"
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e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)"
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e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)"
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e1000e_rx_set_cso(int cso_state) "RX CSO state set to %d"
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e1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u"
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e1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X"
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e1000e_rx_start_recv(void)
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e1000e_rx_rss_started(void) "Starting RSS processing"
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e1000e_rx_rss_disabled(void) "RSS is disabled"
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e1000e_rx_rss_type(uint32_t type) "RSS type is %u"
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e1000e_rx_rss_ip4(bool isfragment, bool istcp, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: fragment %d, tcp %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d"
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e1000e_rx_rss_ip6_rfctl(uint32_t rfctl) "RSS IPv6: rfctl 0x%X"
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e1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, bool istcp, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: ex_dis: %d, new_ex_dis: %d, tcp %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6 enabled %d, ipv6ex enabled %d, ipv6 enabled %d"
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e1000e_rx_rss_dispatched_to_queue(int queue_idx) "Packet being dispatched to queue %d"
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e1000e_rx_metadata_protocols(bool isip4, bool isip6, bool isudp, bool istcp) "protocols: ip4: %d, ip6: %d, udp: %d, tcp: %d"
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e1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X"
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e1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X"
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e1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X"
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e1000e_rx_metadata_ack(void) "the packet is TCP ACK"
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e1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u"
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e1000e_rx_metadata_no_virthdr(void) "the packet has no virt-header"
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e1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info"
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e1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled"
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e1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled"
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e1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum"
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e1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum"
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e1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X"
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e1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL"
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e1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL"
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e1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X"
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e1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x"
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e1000e_irq_throttling_no_pending_interrupts(void) "No pending interrupts to notify"
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e1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR"
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e1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR"
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e1000e_irq_throttling_no_pending_vec(int idx) "No pending interrupts for vector %d"
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e1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]"
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e1000e_irq_legacy_notify(bool level) "IRQ line state: %d"
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e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x"
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e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x"
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e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x"
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e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x"
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e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x"
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e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x"
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e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)"
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e1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ cause 0x%x, ICR: 0x%x"
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e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x"
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e1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing ICR bits 0x%x: 0x%x --> 0x%x"
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e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x"
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e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME"
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e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x"
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e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x"
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e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x"
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e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x"
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e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
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e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME"
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e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X"
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e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X"
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e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x"
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e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts"
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e1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns"
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e1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X"
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e1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running"
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e1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running"
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e1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running"
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e1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running"
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e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u"
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e1000e_irq_itr_set(uint32_t val) "ITR = %u"
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e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)"
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e1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging delayed causes 0x%X to ICR 0x%X"
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e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u"
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e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x"
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e1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x"
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e1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x"
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e1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x"
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# hw/net/e1000e.c
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e1000e_cb_pci_realize(void) "E1000E PCI realize entry"
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e1000e_cb_pci_uninit(void) "E1000E PCI unit entry"
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e1000e_cb_qdev_reset(void) "E1000E qdev reset entry"
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e1000e_cb_pre_save(void) "E1000E pre save entry"
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e1000e_cb_post_load(void) "E1000E post load entry"
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e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64
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e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64
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e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64
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e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64
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e1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64
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e1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64
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e1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64
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e1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented"
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e1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64
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e1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d"
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e1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d"
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e1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d"
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e1000e_cfg_support_virtio(bool support) "Virtio header supported: %d"
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e1000e_vm_state_running(void) "VM state is running"
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e1000e_vm_state_stopped(void) "VM state is stopped"
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# hw/net/spapr_llan.c
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spapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs) "pool=%d count=%"PRId32" rxbufs=%"PRIu32
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spapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd) "use_buf_ptr=%d bd=0x%016"PRIx64
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spapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs) "ptr=%"PRIu32" rxbufs=%"PRIu32
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spapr_vlan_receive(const char *id, uint32_t rx_bufs) "[%s] rx_bufs=%"PRIu32
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spapr_vlan_receive_dma_completed(void) "DMA write completed"
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spapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo) "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64
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spapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len) "created RX pool %d for size %"PRIu64
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spapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count) "add buf using pool %d (size %"PRIu64", count=%"PRId32")"
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spapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd) "added buf ptr=%"PRIu32" rx_bufs=%"PRIu32" bd=0x%016"PRIx64
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spapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf) "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")"
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spapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")"
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spapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) "rxbufs = %"PRIu32
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spapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) " buf desc: 0x%"PRIx64
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spapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) "%d buffers, total length 0x%x"
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# hw/net/sungem.c
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sungem_tx_checksum(uint16_t start, uint16_t off) "TX checksumming from byte %d, inserting at %d"
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sungem_tx_checksum_oob(void) "TX checksum out of packet bounds"
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sungem_tx_unfinished(void) "TX packet started without finishing the previous one"
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sungem_tx_overflow(void) "TX packet queue overflow"
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sungem_tx_finished(uint32_t size) "TX completing %"PRIu32 " bytes packet"
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sungem_tx_kick(void) "TX Kick..."
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sungem_tx_disabled(void) "TX not enabled"
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sungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32
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sungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64
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sungem_tx_reset(void) "TX reset"
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sungem_rx_mac_disabled(void) "Check RX MAC disabled"
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sungem_rx_txdma_disabled(void) "Check RX TXDMA disabled"
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sungem_rx_check(bool full, uint32_t kick, uint32_t done) "Check RX %d (kick=%"PRIu32", done=%"PRIu32")"
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sungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32
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sungem_rx_mac_multicast(void) "Multicast"
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sungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".."
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sungem_rx_packet(size_t size) "RX got %zu bytes packet"
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sungem_rx_disabled(void) "RX not enabled"
|
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sungem_rx_bad_frame_size(size_t size) "RX bad frame size %zu, dropped"
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sungem_rx_unmatched(void) "No match, dropped"
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sungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32
|
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sungem_rx_ringfull(void) "RX ring full"
|
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sungem_rx_desc(uint64_t control, uint64_t buffer) "RX desc: 0x%"PRIx64" 0x%"PRIx64
|
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sungem_rx_reset(void) "RX reset"
|
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sungem_rx_kick(uint64_t val) "RXDMA_KICK written to %"PRIu64
|
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sungem_reset(bool pci_reset) "Full reset (PCI:%d)"
|
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sungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x"
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sungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x"
|
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sungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32
|
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sungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x"
|
|
sungem_mmio_greg_write(uint64_t addr, uint64_t val) "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_greg_read(uint64_t addr, uint64_t val) "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64
|
|
sungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_mif_read(uint64_t addr, uint64_t val) "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_pcs_write(uint64_t addr, uint64_t val) "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64
|
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sungem_mmio_pcs_read(uint64_t addr, uint64_t val) "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64
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