f89ced5f55
Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
409 lines
15 KiB
C
409 lines
15 KiB
C
/*
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* PowerPC memory access emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "helper_regs.h"
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#include "exec/cpu_ldst.h"
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#include "tcg.h"
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#include "internal.h"
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//#define DEBUG_OP
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static inline bool needs_byteswap(const CPUPPCState *env)
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{
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#if defined(TARGET_WORDS_BIGENDIAN)
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return msr_le;
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#else
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return !msr_le;
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#endif
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}
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/*****************************************************************************/
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/* Memory load and stores */
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static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
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target_long arg)
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{
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#if defined(TARGET_PPC64)
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if (!msr_is_64bit(env, env->msr)) {
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return (uint32_t)(addr + arg);
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} else
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#endif
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{
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return addr + arg;
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}
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}
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void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (needs_byteswap(env)) {
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env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
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} else {
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env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
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}
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addr = addr_add(env, addr, 4);
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}
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}
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void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (needs_byteswap(env)) {
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cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
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GETPC());
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} else {
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cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
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}
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addr = addr_add(env, addr, 4);
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}
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}
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static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg, uintptr_t raddr)
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{
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int sh;
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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env->gpr[reg] = 0;
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh;
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addr = addr_add(env, addr, 1);
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}
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}
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}
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void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
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{
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do_lsw(env, addr, nb, reg, GETPC());
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}
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/* PPC32 specification says we must generate an exception if
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* rA is in the range of registers to be loaded.
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* In an other hand, IBM says this is valid, but rA won't be loaded.
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* For now, I'll follow the spec...
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*/
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void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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if (likely(xer_bc != 0)) {
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int num_used_regs = DIV_ROUND_UP(xer_bc, 4);
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if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
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lsw_reg_in_range(reg, num_used_regs, rb))) {
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_INVAL_LSWX, GETPC());
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} else {
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do_lsw(env, addr, xer_bc, reg, GETPC());
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}
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}
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}
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void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg)
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{
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int sh;
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for (; nb > 3; nb -= 4) {
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cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC());
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addr = addr_add(env, addr, 1);
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}
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}
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}
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void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
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{
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target_ulong mask, dcbz_size = env->dcache_line_size;
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uint32_t i;
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void *haddr;
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#if defined(TARGET_PPC64)
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/* Check for dcbz vs dcbzl on 970 */
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if (env->excp_model == POWERPC_EXCP_970 &&
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!(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
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dcbz_size = 32;
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}
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#endif
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/* Align address */
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mask = ~(dcbz_size - 1);
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addr &= mask;
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/* Check reservation */
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if ((env->reserve_addr & mask) == (addr & mask)) {
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env->reserve_addr = (target_ulong)-1ULL;
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}
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/* Try fast path translate */
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haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx);
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if (haddr) {
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memset(haddr, 0, dcbz_size);
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} else {
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/* Slow path */
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for (i = 0; i < dcbz_size; i += 8) {
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cpu_stq_data_ra(env, addr + i, 0, GETPC());
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}
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}
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}
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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{
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addr &= ~(env->dcache_line_size - 1);
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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cpu_ldl_data_ra(env, addr, GETPC());
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}
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/* XXX: to be tested */
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target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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int i, c, d;
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d = 24;
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for (i = 0; i < xer_bc; i++) {
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c = cpu_ldub_data_ra(env, addr, GETPC());
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addr = addr_add(env, addr, 1);
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) {
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env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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}
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if (unlikely(c == xer_cmp)) {
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break;
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}
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if (likely(d != 0)) {
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d -= 8;
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} else {
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d = 24;
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reg++;
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reg = reg & 0x1F;
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}
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}
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return i;
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}
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#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
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uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint32_t opidx)
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{
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Int128 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());
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env->retxh = int128_gethi(ret);
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return int128_getlo(ret);
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}
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void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());
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}
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void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t lo, uint64_t hi, uint32_t opidx)
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{
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Int128 val = int128_make128(lo, hi);
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helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
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}
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#endif
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/*****************************************************************************/
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/* Altivec extension helpers */
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#if defined(HOST_WORDS_BIGENDIAN)
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#define HI_IDX 0
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#define LO_IDX 1
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#else
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#define HI_IDX 1
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#define LO_IDX 0
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#endif
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/* We use msr_le to determine index ordering in a vector. However,
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byteswapping is not simply controlled by msr_le. We also need to take
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into account endianness of the target. This is done for the little-endian
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PPC64 user-mode target. */
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#define LVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \
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int adjust = HI_IDX*(n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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if (msr_le) { \
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index = n_elems - index - 1; \
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} \
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\
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if (needs_byteswap(env)) { \
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r->element[LO_IDX ? index : (adjust - index)] = \
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swap(access(env, addr, GETPC())); \
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} else { \
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r->element[LO_IDX ? index : (adjust - index)] = \
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access(env, addr, GETPC()); \
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} \
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}
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#define I(x) (x)
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LVE(lvebx, cpu_ldub_data_ra, I, u8)
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LVE(lvehx, cpu_lduw_data_ra, bswap16, u16)
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LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
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#undef I
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#undef LVE
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#define STVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \
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int adjust = HI_IDX * (n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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if (msr_le) { \
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index = n_elems - index - 1; \
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} \
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\
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if (needs_byteswap(env)) { \
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access(env, addr, swap(r->element[LO_IDX ? index : \
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(adjust - index)]), \
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GETPC()); \
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} else { \
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access(env, addr, r->element[LO_IDX ? index : \
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(adjust - index)], GETPC()); \
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} \
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}
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#define I(x) (x)
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STVE(stvebx, cpu_stb_data_ra, I, u8)
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STVE(stvehx, cpu_stw_data_ra, bswap16, u16)
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STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
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#undef I
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#undef LVE
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#ifdef TARGET_PPC64
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#define GET_NB(rb) ((rb >> 56) & 0xFF)
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#define VSX_LXVL(name, lj) \
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void helper_##name(CPUPPCState *env, target_ulong addr, \
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target_ulong xt_num, target_ulong rb) \
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{ \
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int i; \
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ppc_vsr_t xt; \
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uint64_t nb = GET_NB(rb); \
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\
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xt.s128 = int128_zero(); \
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if (nb) { \
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nb = (nb >= 16) ? 16 : nb; \
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if (msr_le && !lj) { \
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for (i = 16; i > 16 - nb; i--) { \
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xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
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addr = addr_add(env, addr, 1); \
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} \
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} else { \
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for (i = 0; i < nb; i++) { \
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xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
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addr = addr_add(env, addr, 1); \
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} \
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} \
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} \
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putVSR(xt_num, &xt, env); \
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}
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VSX_LXVL(lxvl, 0)
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VSX_LXVL(lxvll, 1)
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#undef VSX_LXVL
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#define VSX_STXVL(name, lj) \
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void helper_##name(CPUPPCState *env, target_ulong addr, \
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target_ulong xt_num, target_ulong rb) \
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{ \
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int i; \
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ppc_vsr_t xt; \
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target_ulong nb = GET_NB(rb); \
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\
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if (!nb) { \
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return; \
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} \
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getVSR(xt_num, &xt, env); \
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nb = (nb >= 16) ? 16 : nb; \
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if (msr_le && !lj) { \
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for (i = 16; i > 16 - nb; i--) { \
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cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \
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addr = addr_add(env, addr, 1); \
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} \
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} else { \
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for (i = 0; i < nb; i++) { \
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cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \
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addr = addr_add(env, addr, 1); \
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} \
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} \
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}
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VSX_STXVL(stxvl, 0)
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VSX_STXVL(stxvll, 1)
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#undef VSX_STXVL
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#undef GET_NB
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#endif /* TARGET_PPC64 */
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#undef HI_IDX
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#undef LO_IDX
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void helper_tbegin(CPUPPCState *env)
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{
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/* As a degenerate implementation, always fail tbegin. The reason
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* given is "Nesting overflow". The "persistent" bit is set,
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* providing a hint to the error handler to not retry. The TFIAR
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* captures the address of the failure, which is this tbegin
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* instruction. Instruction execution will continue with the
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* next instruction in memory, which is precisely what we want.
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*/
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env->spr[SPR_TEXASR] =
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(1ULL << TEXASR_FAILURE_PERSISTENT) |
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(1ULL << TEXASR_NESTING_OVERFLOW) |
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(msr_hv << TEXASR_PRIVILEGE_HV) |
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(msr_pr << TEXASR_PRIVILEGE_PR) |
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(1ULL << TEXASR_FAILURE_SUMMARY) |
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(1ULL << TEXASR_TFIAR_EXACT);
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env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
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env->spr[SPR_TFHAR] = env->nip + 4;
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env->crf[0] = 0xB; /* 0b1010 = transaction failure */
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}
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