345 lines
9.3 KiB
C
345 lines
9.3 KiB
C
/*
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* Intel XScale PXA255/270 GPIO controller emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPL.
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*/
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#include "hw.h"
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#include "pxa.h"
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#define PXA2XX_GPIO_BANKS 4
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struct PXA2xxGPIOInfo {
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qemu_irq *pic;
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int lines;
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CPUState *cpu_env;
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qemu_irq *in;
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/* XXX: GNU C vectors are more suitable */
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uint32_t ilevel[PXA2XX_GPIO_BANKS];
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uint32_t olevel[PXA2XX_GPIO_BANKS];
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uint32_t dir[PXA2XX_GPIO_BANKS];
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uint32_t rising[PXA2XX_GPIO_BANKS];
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uint32_t falling[PXA2XX_GPIO_BANKS];
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uint32_t status[PXA2XX_GPIO_BANKS];
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uint32_t gpsr[PXA2XX_GPIO_BANKS];
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uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
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uint32_t prev_level[PXA2XX_GPIO_BANKS];
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qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
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qemu_irq read_notify;
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};
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static struct {
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enum {
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GPIO_NONE,
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GPLR,
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GPSR,
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GPCR,
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GPDR,
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GRER,
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GFER,
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GEDR,
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GAFR_L,
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GAFR_U,
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} reg;
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int bank;
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} pxa2xx_gpio_regs[0x200] = {
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[0 ... 0x1ff] = { GPIO_NONE, 0 },
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#define PXA2XX_REG(reg, a0, a1, a2, a3) \
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[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
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PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
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PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
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PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
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PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
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PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
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PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
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PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
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PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
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PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
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};
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static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
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{
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if (s->status[0] & (1 << 0))
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qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
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else
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qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
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if (s->status[0] & (1 << 1))
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qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
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else
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qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
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if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
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qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
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else
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qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
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}
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/* Bitmap of pins used as standby and sleep wake-up sources. */
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static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
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0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
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};
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static void pxa2xx_gpio_set(void *opaque, int line, int level)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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int bank;
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uint32_t mask;
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if (line >= s->lines) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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}
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bank = line >> 5;
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mask = 1 << (line & 31);
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if (level) {
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s->status[bank] |= s->rising[bank] & mask &
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~s->ilevel[bank] & ~s->dir[bank];
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s->ilevel[bank] |= mask;
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} else {
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s->status[bank] |= s->falling[bank] & mask &
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s->ilevel[bank] & ~s->dir[bank];
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s->ilevel[bank] &= ~mask;
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}
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if (s->status[bank] & mask)
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pxa2xx_gpio_irq_update(s);
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/* Wake-up GPIOs */
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if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
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}
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static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
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uint32_t level, diff;
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int i, bit, line;
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for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
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level = s->olevel[i] & s->dir[i];
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for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
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bit = ffs(diff) - 1;
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line = bit + 32 * i;
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qemu_set_irq(s->handler[line], (level >> bit) & 1);
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}
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s->prev_level[i] = level;
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}
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}
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static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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uint32_t ret;
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int bank;
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if (offset >= 0x200)
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return 0;
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bank = pxa2xx_gpio_regs[offset].bank;
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switch (pxa2xx_gpio_regs[offset].reg) {
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case GPDR: /* GPIO Pin-Direction registers */
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return s->dir[bank];
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case GPSR: /* GPIO Pin-Output Set registers */
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printf("%s: Read from a write-only register " REG_FMT "\n",
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__FUNCTION__, offset);
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return s->gpsr[bank]; /* Return last written value. */
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case GPCR: /* GPIO Pin-Output Clear registers */
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printf("%s: Read from a write-only register " REG_FMT "\n",
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__FUNCTION__, offset);
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return 31337; /* Specified as unpredictable in the docs. */
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case GRER: /* GPIO Rising-Edge Detect Enable registers */
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return s->rising[bank];
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case GFER: /* GPIO Falling-Edge Detect Enable registers */
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return s->falling[bank];
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case GAFR_L: /* GPIO Alternate Function registers */
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return s->gafr[bank * 2];
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case GAFR_U: /* GPIO Alternate Function registers */
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return s->gafr[bank * 2 + 1];
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case GPLR: /* GPIO Pin-Level registers */
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ret = (s->olevel[bank] & s->dir[bank]) |
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(s->ilevel[bank] & ~s->dir[bank]);
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qemu_irq_raise(s->read_notify);
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return ret;
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case GEDR: /* GPIO Edge Detect Status registers */
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return s->status[bank];
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
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}
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return 0;
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}
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static void pxa2xx_gpio_write(void *opaque,
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target_phys_addr_t offset, uint32_t value)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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int bank;
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if (offset >= 0x200)
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return;
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bank = pxa2xx_gpio_regs[offset].bank;
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switch (pxa2xx_gpio_regs[offset].reg) {
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case GPDR: /* GPIO Pin-Direction registers */
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s->dir[bank] = value;
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pxa2xx_gpio_handler_update(s);
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break;
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case GPSR: /* GPIO Pin-Output Set registers */
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s->olevel[bank] |= value;
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pxa2xx_gpio_handler_update(s);
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s->gpsr[bank] = value;
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break;
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case GPCR: /* GPIO Pin-Output Clear registers */
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s->olevel[bank] &= ~value;
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pxa2xx_gpio_handler_update(s);
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break;
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case GRER: /* GPIO Rising-Edge Detect Enable registers */
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s->rising[bank] = value;
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break;
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case GFER: /* GPIO Falling-Edge Detect Enable registers */
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s->falling[bank] = value;
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break;
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case GAFR_L: /* GPIO Alternate Function registers */
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s->gafr[bank * 2] = value;
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break;
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case GAFR_U: /* GPIO Alternate Function registers */
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s->gafr[bank * 2 + 1] = value;
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break;
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case GEDR: /* GPIO Edge Detect Status registers */
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s->status[bank] &= ~value;
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pxa2xx_gpio_irq_update(s);
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break;
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
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}
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}
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static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
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pxa2xx_gpio_read,
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pxa2xx_gpio_read,
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pxa2xx_gpio_read
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};
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static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
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pxa2xx_gpio_write,
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pxa2xx_gpio_write,
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pxa2xx_gpio_write
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};
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static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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int i;
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qemu_put_be32(f, s->lines);
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for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
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qemu_put_be32s(f, &s->ilevel[i]);
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qemu_put_be32s(f, &s->olevel[i]);
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qemu_put_be32s(f, &s->dir[i]);
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qemu_put_be32s(f, &s->rising[i]);
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qemu_put_be32s(f, &s->falling[i]);
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qemu_put_be32s(f, &s->status[i]);
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qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
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qemu_put_be32s(f, &s->gafr[i * 2 + 1]);
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qemu_put_be32s(f, &s->prev_level[i]);
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}
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}
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static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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int i;
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if (qemu_get_be32(f) != s->lines)
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return -EINVAL;
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for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
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qemu_get_be32s(f, &s->ilevel[i]);
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qemu_get_be32s(f, &s->olevel[i]);
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qemu_get_be32s(f, &s->dir[i]);
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qemu_get_be32s(f, &s->rising[i]);
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qemu_get_be32s(f, &s->falling[i]);
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qemu_get_be32s(f, &s->status[i]);
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qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
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qemu_get_be32s(f, &s->gafr[i * 2 + 1]);
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qemu_get_be32s(f, &s->prev_level[i]);
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}
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return 0;
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}
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PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, qemu_irq *pic, int lines)
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{
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int iomemtype;
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PXA2xxGPIOInfo *s;
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s = (PXA2xxGPIOInfo *)
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qemu_mallocz(sizeof(PXA2xxGPIOInfo));
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memset(s, 0, sizeof(PXA2xxGPIOInfo));
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s->pic = pic;
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s->lines = lines;
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s->cpu_env = env;
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s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
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iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
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pxa2xx_gpio_writefn, s);
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cpu_register_physical_memory(base, 0x00001000, iomemtype);
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register_savevm("pxa2xx_gpio", 0, 0,
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pxa2xx_gpio_save, pxa2xx_gpio_load, s);
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return s;
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}
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qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s)
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{
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return s->in;
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}
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void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
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int line, qemu_irq handler)
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{
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if (line >= s->lines) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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}
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s->handler[line] = handler;
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}
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/*
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* Registers a callback to notify on GPLR reads. This normally
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* shouldn't be needed but it is used for the hack on Spitz machines.
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*/
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void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler)
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{
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s->read_notify = handler;
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}
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