qemu-e2k/target
Nicholas Piggin f9e3e1a35e target/ppc: Fix slbia TLB invalidation gap
slbia must invalidate TLBs even if it does not remove a valid SLB
entry, because slbmte can overwrite valid entries without removing
their TLBs.

As the architecture says, slbia invalidates all lookaside information,
not conditionally based on if it removed valid entries.

It does not seem possible for POWER8 or earlier Linux kernels to hit
this bug because it never changes its kernel SLB translations, and it
should always have valid entries if any accesses are made to userspace
regions. However other operating systems which may modify SLB entry 0
or do more fancy things with segments might be affected.

When POWER9 slbia support is added in the next patch, this becomes a
real problem because some new slbia variants don't invalidate all
non-zero entries.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20200318044135.851716-1-npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-03-24 11:05:37 +11:00
..
alpha x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
arm target/arm: Move computation of index in handle_simd_dupe 2020-03-23 17:22:30 +00:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
i386 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
microblaze x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
mips x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
ppc target/ppc: Fix slbia TLB invalidation gap 2020-03-24 11:05:37 +11:00
riscv x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
rx target/rx: Dump bytes for each insn during disassembly 2020-03-19 17:58:05 +01:00
s390x x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sh4 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
sparc x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
unicore32 tcg: Search includes from the project root source directory 2020-01-15 15:13:10 -10:00
xtensa x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00