Stefan Markovic fa192d4974 target/mips: Implement CP0 Config1.WR bit functionality ... Add testing Config1.WR bit into watch exception handling logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>		2018-08-16 19:18:45 +02:00
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alpha
arm	target/arm: Fix typo in helper_sve_movz_d	2018-08-14 17:17:22 +01:00
cris
hppa
i386	i386: implement MSR_SMI_COUNT for TCG	2018-07-30 14:00:11 +02:00
lm32
m68k
microblaze
mips	target/mips: Implement CP0 Config1.WR bit functionality	2018-08-16 19:18:45 +02:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc: fix build on ppc64 host	2018-07-07 12:12:27 +10:00
riscv
s390x	s390x/cpumodel: fix segmentation fault when baselining models	2018-07-18 14:20:02 +02:00
sh4	target/sh4: Fix translator.c assertion failure for gUSA	2018-07-09 10:34:04 -07:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32
xtensa	target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn	2018-08-06 19:07:21 +01:00