269 lines
6.7 KiB
C++
269 lines
6.7 KiB
C++
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*
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* Based on tcg/riscv/tcg-target.c.inc
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*
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* Copyright (c) 2018 SiFive, Inc
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifdef CONFIG_DEBUG_TCG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"zero",
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"ra",
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"tp",
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"sp",
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"a0",
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"a1",
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"a2",
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"a3",
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"a4",
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"a5",
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"a6",
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"a7",
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"t0",
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"t1",
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"t2",
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"t3",
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"t4",
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"t5",
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"t6",
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"t7",
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"t8",
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"r21", /* reserved in the LP64* ABI, hence no ABI name */
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"s9",
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"s0",
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"s1",
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"s2",
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"s3",
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"s4",
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"s5",
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"s6",
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"s7",
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"s8"
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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/* Registers preserved across calls */
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/* TCG_REG_S0 reserved for TCG_AREG0 */
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_S8,
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TCG_REG_S9,
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/* Registers (potentially) clobbered across calls */
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TCG_REG_T0,
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TCG_REG_T1,
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TCG_REG_T2,
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TCG_REG_T3,
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TCG_REG_T4,
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TCG_REG_T5,
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TCG_REG_T6,
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TCG_REG_T7,
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TCG_REG_T8,
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/* Argument registers, opposite order of allocation. */
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TCG_REG_A7,
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TCG_REG_A6,
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TCG_REG_A5,
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TCG_REG_A4,
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TCG_REG_A3,
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TCG_REG_A2,
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TCG_REG_A1,
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TCG_REG_A0,
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};
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static const int tcg_target_call_iarg_regs[] = {
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TCG_REG_A0,
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TCG_REG_A1,
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TCG_REG_A2,
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TCG_REG_A3,
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TCG_REG_A4,
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TCG_REG_A5,
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TCG_REG_A6,
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TCG_REG_A7,
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};
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static const int tcg_target_call_oarg_regs[] = {
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TCG_REG_A0,
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TCG_REG_A1,
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};
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#define TCG_CT_CONST_ZERO 0x100
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#define TCG_CT_CONST_S12 0x200
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#define TCG_CT_CONST_N12 0x400
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#define TCG_CT_CONST_U12 0x800
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#define TCG_CT_CONST_C12 0x1000
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#define TCG_CT_CONST_WSZ 0x2000
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#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
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/*
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* For softmmu, we need to avoid conflicts with the first 5
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* argument registers to call the helper. Some of these are
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* also used for the tlb lookup.
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*/
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#ifdef CONFIG_SOFTMMU
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#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5)
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#else
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#define SOFTMMU_RESERVE_REGS 0
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#endif
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static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
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{
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return sextract64(val, pos, len);
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}
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/* test if a constant matches the constraint */
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static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
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{
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if (ct & TCG_CT_CONST) {
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return true;
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}
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if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
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return true;
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}
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if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
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return true;
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}
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if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
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return true;
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}
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if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
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return true;
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}
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if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
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return true;
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}
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if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
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return true;
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}
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return false;
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}
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/*
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* Relocations
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*/
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/*
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* Relocation records defined in LoongArch ELF psABI v1.00 is way too
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* complicated; a whopping stack machine is needed to stuff the fields, at
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* the very least one SOP_PUSH and one SOP_POP (of the correct format) are
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* needed.
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*
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* Hence, define our own simpler relocation types. Numbers are chosen as to
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* not collide with potential future additions to the true ELF relocation
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* type enum.
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*/
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/* Field Sk16, shifted right by 2; suitable for conditional jumps */
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#define R_LOONGARCH_BR_SK16 256
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/* Field Sd10k16, shifted right by 2; suitable for B and BL */
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#define R_LOONGARCH_BR_SD10K16 257
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static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
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{
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const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
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intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
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tcg_debug_assert((offset & 3) == 0);
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offset >>= 2;
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if (offset == sextreg(offset, 0, 16)) {
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*src_rw = deposit64(*src_rw, 10, 16, offset);
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return true;
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}
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return false;
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}
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static bool reloc_br_sd10k16(tcg_insn_unit *src_rw,
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const tcg_insn_unit *target)
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{
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const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
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intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
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tcg_debug_assert((offset & 3) == 0);
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offset >>= 2;
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if (offset == sextreg(offset, 0, 26)) {
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*src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */
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*src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */
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return true;
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}
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return false;
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}
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static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend)
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{
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tcg_debug_assert(addend == 0);
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switch (type) {
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case R_LOONGARCH_BR_SK16:
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return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value);
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case R_LOONGARCH_BR_SD10K16:
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return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value);
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default:
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g_assert_not_reached();
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}
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}
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#include "tcg-insn-defs.c.inc"
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/*
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* TCG intrinsics
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*/
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static void tcg_out_mb(TCGContext *s, TCGArg a0)
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{
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/* Baseline LoongArch only has the full barrier, unfortunately. */
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tcg_out_opc_dbar(s, 0);
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}
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/*
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* Entry-points
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*/
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg args[TCG_MAX_OP_ARGS],
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const int const_args[TCG_MAX_OP_ARGS])
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{
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TCGArg a0 = args[0];
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switch (opc) {
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case INDEX_op_mb:
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tcg_out_mb(s, a0);
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break;
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default:
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g_assert_not_reached();
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}
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}
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