Daniel Henrique Barboza fafb0dc4d4 target/riscv/kvm: change kvm_reg_id to uint64_t ... The field isn't big enough to hold an uint64_t kvm register and Vector registers will end up overflowing it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240123161714.160149-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-02-09 20:43:14 +10:00
..
insn_trans	trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()	2024-02-09 20:43:14 +10:00
kvm	target/riscv/kvm: change kvm_reg_id to uint64_t	2024-02-09 20:43:14 +10:00
tcg	target/riscv/cpu.c: remove cpu->cfg.vlen	2024-02-09 20:43:14 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
cpu_cfg.h	target/riscv/cpu.c: remove cpu->cfg.vlen	2024-02-09 20:43:14 +10:00
cpu_helper.c	target/riscv: change vext_get_vlmax() arguments	2024-02-09 20:43:14 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rva22s64 cpu	2024-01-10 18:47:47 +10:00
cpu.c	target/riscv/cpu.c: remove cpu->cfg.vlen	2024-02-09 20:43:14 +10:00
cpu.h	target/riscv: change vext_get_vlmax() arguments	2024-02-09 20:43:14 +10:00
crypto_helper.c
csr.c	target/riscv/csr.c: use 'vlenb' instead of 'vlen'	2024-02-09 20:43:14 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c	target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'	2024-02-09 20:43:14 +10:00
helper.h
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h
Kconfig
m128_helper.c
machine.c	target/riscv: Constify VMState in machine.c	2023-12-29 11:17:30 +11:00
meson.build
monitor.c
op_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01 and MML=0	2024-01-10 18:47:47 +10:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c
pmu.h
riscv-qmp-cmds.c	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target: Use vaddr in gen_intermediate_code	2024-01-29 07:06:03 +10:00
vcrypto_helper.c
vector_helper.c	target/riscv: change vext_get_vlmax() arguments	2024-02-09 20:43:14 +10:00
vector_internals.c	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
vector_internals.h	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c