fb43cf739e
Intel(R) VT-d 3.0 spec introduces scalable mode address translation to replace extended context mode. This patch extends current emulator to support Scalable Mode which includes root table, context table and new pasid table format change. Now intel_iommu emulates both legacy mode and scalable mode (with legacy-equivalent capability set). The key points are below: 1. Extend root table operations to support both legacy mode and scalable mode. 2. Extend context table operations to support both legacy mode and scalable mode. 3. Add pasid tabled operations to support scalable mode. Signed-off-by: Liu, Yi L <yi.l.liu@intel.com> [Yi Sun is co-developer to contribute much to refine the whole commit.] Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Message-Id: <1551753295-30167-2-git-send-email-yi.y.sun@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com>
283 lines
10 KiB
C
283 lines
10 KiB
C
/*
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* QEMU emulation of an Intel IOMMU (VT-d)
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* (DMA Remapping device)
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*
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* Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
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* Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INTEL_IOMMU_H
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#define INTEL_IOMMU_H
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#include "hw/qdev.h"
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#include "sysemu/dma.h"
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#include "hw/i386/x86-iommu.h"
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#include "hw/i386/ioapic.h"
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#include "hw/pci/msi.h"
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#include "hw/sysbus.h"
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#include "qemu/iova-tree.h"
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#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
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#define INTEL_IOMMU_DEVICE(obj) \
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OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
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#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
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/* DMAR Hardware Unit Definition address (IOMMU unit) */
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#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
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#define VTD_PCI_BUS_MAX 256
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#define VTD_PCI_SLOT_MAX 32
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#define VTD_PCI_FUNC_MAX 8
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#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
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#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
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#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
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#define DMAR_REG_SIZE 0x230
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#define VTD_HOST_AW_39BIT 39
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#define VTD_HOST_AW_48BIT 48
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#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
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#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
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#define DMAR_REPORT_F_INTR (1)
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#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
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#define VTD_MSI_ADDR_HI_SHIFT (32)
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#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
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typedef struct VTDContextEntry VTDContextEntry;
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typedef struct VTDContextCacheEntry VTDContextCacheEntry;
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typedef struct IntelIOMMUState IntelIOMMUState;
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typedef struct VTDAddressSpace VTDAddressSpace;
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typedef struct VTDIOTLBEntry VTDIOTLBEntry;
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typedef struct VTDBus VTDBus;
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typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
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typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
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typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
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typedef struct VTDPASIDEntry VTDPASIDEntry;
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/* Context-Entry */
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struct VTDContextEntry {
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union {
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struct {
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uint64_t lo;
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uint64_t hi;
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};
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struct {
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uint64_t val[4];
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};
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};
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};
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struct VTDContextCacheEntry {
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/* The cache entry is obsolete if
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* context_cache_gen!=IntelIOMMUState.context_cache_gen
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*/
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uint32_t context_cache_gen;
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struct VTDContextEntry context_entry;
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};
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/* PASID Directory Entry */
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struct VTDPASIDDirEntry {
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uint64_t val;
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};
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/* PASID Table Entry */
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struct VTDPASIDEntry {
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uint64_t val[8];
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};
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struct VTDAddressSpace {
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PCIBus *bus;
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uint8_t devfn;
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AddressSpace as;
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IOMMUMemoryRegion iommu;
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MemoryRegion root;
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MemoryRegion sys_alias;
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MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
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IntelIOMMUState *iommu_state;
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VTDContextCacheEntry context_cache_entry;
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QLIST_ENTRY(VTDAddressSpace) next;
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/* Superset of notifier flags that this address space has */
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IOMMUNotifierFlag notifier_flags;
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IOVATree *iova_tree; /* Traces mapped IOVA ranges */
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};
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struct VTDBus {
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PCIBus* bus; /* A reference to the bus to provide translation for */
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VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
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};
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struct VTDIOTLBEntry {
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uint64_t gfn;
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uint16_t domain_id;
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uint64_t slpte;
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uint64_t mask;
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uint8_t access_flags;
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};
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/* VT-d Source-ID Qualifier types */
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enum {
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VTD_SQ_FULL = 0x00, /* Full SID verification */
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VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
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VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
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VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
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VTD_SQ_MAX,
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};
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/* VT-d Source Validation Types */
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enum {
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VTD_SVT_NONE = 0x00, /* No validation */
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VTD_SVT_ALL = 0x01, /* Do full validation */
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VTD_SVT_BUS = 0x02, /* Validate bus range */
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VTD_SVT_MAX,
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};
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/* Interrupt Remapping Table Entry Definition */
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union VTD_IR_TableEntry {
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struct {
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#ifdef HOST_WORDS_BIGENDIAN
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uint32_t __reserved_1:8; /* Reserved 1 */
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uint32_t vector:8; /* Interrupt Vector */
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uint32_t irte_mode:1; /* IRTE Mode */
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uint32_t __reserved_0:3; /* Reserved 0 */
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uint32_t __avail:4; /* Available spaces for software */
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uint32_t delivery_mode:3; /* Delivery Mode */
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uint32_t trigger_mode:1; /* Trigger Mode */
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uint32_t redir_hint:1; /* Redirection Hint */
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uint32_t dest_mode:1; /* Destination Mode */
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uint32_t fault_disable:1; /* Fault Processing Disable */
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uint32_t present:1; /* Whether entry present/available */
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#else
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uint32_t present:1; /* Whether entry present/available */
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uint32_t fault_disable:1; /* Fault Processing Disable */
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uint32_t dest_mode:1; /* Destination Mode */
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uint32_t redir_hint:1; /* Redirection Hint */
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uint32_t trigger_mode:1; /* Trigger Mode */
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uint32_t delivery_mode:3; /* Delivery Mode */
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uint32_t __avail:4; /* Available spaces for software */
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uint32_t __reserved_0:3; /* Reserved 0 */
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uint32_t irte_mode:1; /* IRTE Mode */
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uint32_t vector:8; /* Interrupt Vector */
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uint32_t __reserved_1:8; /* Reserved 1 */
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#endif
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uint32_t dest_id; /* Destination ID */
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uint16_t source_id; /* Source-ID */
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#ifdef HOST_WORDS_BIGENDIAN
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uint64_t __reserved_2:44; /* Reserved 2 */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t sid_q:2; /* Source-ID Qualifier */
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#else
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uint64_t sid_q:2; /* Source-ID Qualifier */
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uint64_t sid_vtype:2; /* Source-ID Validation Type */
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uint64_t __reserved_2:44; /* Reserved 2 */
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#endif
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} QEMU_PACKED irte;
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uint64_t data[2];
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};
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#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
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#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
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/* Programming format for MSI/MSI-X addresses */
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union VTD_IR_MSIAddress {
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struct {
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#ifdef HOST_WORDS_BIGENDIAN
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uint32_t __head:12; /* Should always be: 0x0fee */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t __not_care:2;
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#else
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uint32_t __not_care:2;
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uint32_t index_h:1; /* Interrupt index bit 15 */
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uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
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uint32_t int_mode:1; /* Interrupt format */
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uint32_t index_l:15; /* Interrupt index bit 14-0 */
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uint32_t __head:12; /* Should always be: 0x0fee */
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#endif
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} QEMU_PACKED addr;
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uint32_t data;
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};
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/* When IR is enabled, all MSI/MSI-X data bits should be zero */
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#define VTD_IR_MSI_DATA (0)
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/* The iommu (DMAR) device state struct */
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struct IntelIOMMUState {
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X86IOMMUState x86_iommu;
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MemoryRegion csrmem;
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uint8_t csr[DMAR_REG_SIZE]; /* register values */
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uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
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uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
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uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
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uint32_t version;
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bool caching_mode; /* RO - is cap CM enabled? */
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dma_addr_t root; /* Current root table pointer */
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bool root_extended; /* Type of root table (extended or not) */
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bool root_scalable; /* Type of root table (scalable or not) */
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bool dmar_enabled; /* Set if DMA remapping is enabled */
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uint16_t iq_head; /* Current invalidation queue head */
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uint16_t iq_tail; /* Current invalidation queue tail */
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dma_addr_t iq; /* Current invalidation queue pointer */
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uint16_t iq_size; /* IQ Size in number of entries */
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bool qi_enabled; /* Set if the QI is enabled */
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uint8_t iq_last_desc_type; /* The type of last completed descriptor */
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/* The index of the Fault Recording Register to be used next.
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* Wraps around from N-1 to 0, where N is the number of FRCD_REG.
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*/
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uint16_t next_frcd_reg;
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uint64_t cap; /* The value of capability reg */
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uint64_t ecap; /* The value of extended capability reg */
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uint32_t context_cache_gen; /* Should be in [1,MAX] */
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GHashTable *iotlb; /* IOTLB */
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GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
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VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
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/* list of registered notifiers */
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QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
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/* interrupt remapping */
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bool intr_enabled; /* Whether guest enabled IR */
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dma_addr_t intr_root; /* Interrupt remapping table pointer */
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uint32_t intr_size; /* Number of IR table entries */
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bool intr_eime; /* Extended interrupt mode enabled */
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OnOffAuto intr_eim; /* Toggle for EIM cabability */
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bool buggy_eim; /* Force buggy EIM unless eim=off */
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uint8_t aw_bits; /* Host/IOVA address width (in bits) */
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bool dma_drain; /* Whether DMA r/w draining enabled */
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/*
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* Protects IOMMU states in general. Currently it protects the
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* per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
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*/
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QemuMutex iommu_lock;
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};
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/* Find the VTD Address space associated with the given bus pointer,
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* create a new one if none exists
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*/
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VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
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#endif
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