Cameron Esfahani fbafbb6db7 hvf: non-RAM, non-ROMD memory ranges are now correctly mapped in ... If an area is non-RAM and non-ROMD, then remove mappings so accesses will trap and can be emulated. Change hvf_find_overlap_slot() to take a size instead of an end address: it wouldn't return a slot because callers would pass the same address for start and end. Don't always map area as read/write/execute, respect area flags. Signed-off-by: Cameron Esfahani <dirty@apple.com> Message-Id: <1d8476c8f86959273fbdf23c86f8b4b611f5e2e1.1574625592.git.dirty@apple.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-11-26 09:58:33 +01:00
..
alpha	target/alpha: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
arm	target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY	2019-11-19 13:20:28 +00:00
cris	cputlb: ensure _cmmu helper functions follow the naming standard	2019-10-28 15:12:38 +00:00
hppa	target/hppa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
i386	hvf: non-RAM, non-ROMD memory ranges are now correctly mapped in	2019-11-26 09:58:33 +01:00
lm32
m68k	target/m68k: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
microblaze	target/microblaze: Plug temp leak around eval_cond_jmp()	2019-11-12 16:35:26 +01:00
mips	target/mips: Refactor handling of vector compare 'less than' (signed) instructions	2019-10-25 18:37:01 +02:00
moxie
nios2
openrisc	target/openrisc: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
ppc	spapr/kvm: Set default cpu model for all machine classes	2019-11-18 11:50:39 +01:00
riscv	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4	target/sh4: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
sparc	target/sparc: Define an enumeration for accessing env->regwptr	2019-11-06 13:35:25 +01:00
tilegx
tricore
unicore32
xtensa	target/xtensa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00