6f5bb7d405
The Sv32 page-based virtual-memory scheme described in RISCV privileged spec Section 5.3 supports 34-bit physical addresses for RV32, so the PMP scheme must support addresses wider than XLEN for RV32. However, PMP address register format is still 32 bit wide. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231123091214.20312-1-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* QEMU RISC-V PMP (Physical Memory Protection)
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*
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* Author: Daire McNamara, daire.mcnamara@emdalo.com
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* Ivan Griffin, ivan.griffin@emdalo.com
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*
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* This provides a RISC-V Physical Memory Protection interface
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_PMP_H
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#define RISCV_PMP_H
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#include "cpu.h"
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typedef enum {
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PMP_READ = 1 << 0,
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PMP_WRITE = 1 << 1,
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PMP_EXEC = 1 << 2,
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PMP_AMATCH = (3 << 3),
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PMP_LOCK = 1 << 7
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} pmp_priv_t;
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typedef enum {
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PMP_AMATCH_OFF, /* Null (off) */
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PMP_AMATCH_TOR, /* Top of Range */
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PMP_AMATCH_NA4, /* Naturally aligned four-byte region */
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PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
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} pmp_am_t;
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typedef enum {
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MSECCFG_MML = 1 << 0,
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MSECCFG_MMWP = 1 << 1,
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MSECCFG_RLB = 1 << 2,
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MSECCFG_USEED = 1 << 8,
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MSECCFG_SSEED = 1 << 9
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} mseccfg_field_t;
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typedef struct {
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target_ulong addr_reg;
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uint8_t cfg_reg;
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} pmp_entry_t;
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typedef struct {
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hwaddr sa;
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hwaddr ea;
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} pmp_addr_t;
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typedef struct {
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pmp_entry_t pmp[MAX_RISCV_PMPS];
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pmp_addr_t addr[MAX_RISCV_PMPS];
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uint32_t num_rules;
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} pmp_table_t;
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void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
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target_ulong val);
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target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
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void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
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target_ulong mseccfg_csr_read(CPURISCVState *env);
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void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong val);
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target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
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bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
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target_ulong size, pmp_priv_t privs,
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pmp_priv_t *allowed_privs,
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target_ulong mode);
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target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
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void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
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void pmp_update_rule_nums(CPURISCVState *env);
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uint32_t pmp_get_num_rules(CPURISCVState *env);
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int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
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void pmp_unlock_entries(CPURISCVState *env);
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#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
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#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
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#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
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#endif
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