ba1ba5cca3
there are 2 use cases to deal with:
1: fixed CPU models per board/soc
2: boards with user configurable cpu_model and fallback to
default cpu_model if user hasn't specified one explicitly
For the 1st
drop intermediate cpu_model parsing and use const cpu type
directly, which replaces:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
object_new(typename)
with
object_new(FOO_CPU_TYPE_NAME)
or
cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
with
cpu_create(FOO_CPU_TYPE_NAME)
as result 1st use case doesn't have to invoke not necessary
translation and not needed code is removed.
For the 2nd
1: set default cpu type with MachineClass::default_cpu_type and
2: use generic cpu_model parsing that done before machine_init()
is run and:
2.1: drop custom cpu_model parsing where pattern is:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
[parse_features(typename, cpu_model, &err) ]
2.2: or replace cpu_generic_init() which does what
2.1 does + create_cpu(typename) with just
create_cpu(machine->cpu_type)
as result cpu_name -> cpu_type translation is done using
generic machine code one including parsing optional features
if supported/present (removes a bunch of duplicated cpu_model
parsing code) and default cpu type is defined in an uniform way
within machine_class_init callbacks instead of adhoc places
in boadr's machine_init code.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1505318697-77161-6-git-send-email-imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
383 lines
14 KiB
C
383 lines
14 KiB
C
/*
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* ARM V2M MPS2 board emulation.
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
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* FPGA but is otherwise the same as the 2). Since the CPU itself
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* and most of the devices are in the FPGA, the details of the board
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* as seen by the guest depend significantly on the FPGA image.
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* We model the following FPGA images:
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* "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
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* "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
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*
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* Links to the TRM for the board itself and to the various Application
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* Notes which document the FPGA images can be found here:
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* https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/arm/arm.h"
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#include "hw/arm/armv7m.h"
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#include "hw/or-irq.h"
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#include "hw/boards.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/misc/unimp.h"
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#include "hw/char/cmsdk-apb-uart.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "hw/misc/mps2-scc.h"
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#include "hw/devices.h"
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#include "net/net.h"
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typedef enum MPS2FPGAType {
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FPGA_AN385,
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FPGA_AN511,
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} MPS2FPGAType;
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typedef struct {
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MachineClass parent;
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MPS2FPGAType fpga_type;
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uint32_t scc_id;
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} MPS2MachineClass;
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typedef struct {
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MachineState parent;
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ARMv7MState armv7m;
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MemoryRegion psram;
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MemoryRegion ssram1;
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MemoryRegion ssram1_m;
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MemoryRegion ssram23;
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MemoryRegion ssram23_m;
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MemoryRegion blockram;
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MemoryRegion blockram_m1;
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MemoryRegion blockram_m2;
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MemoryRegion blockram_m3;
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MemoryRegion sram;
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MPS2SCC scc;
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} MPS2MachineState;
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#define TYPE_MPS2_MACHINE "mps2"
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#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
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#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
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#define MPS2_MACHINE(obj) \
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OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
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#define MPS2_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
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#define MPS2_MACHINE_CLASS(klass) \
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OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
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/* Main SYSCLK frequency in Hz */
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#define SYSCLK_FRQ 25000000
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/* Initialize the auxiliary RAM region @mr and map it into
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* the memory map at @base.
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*/
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static void make_ram(MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size)
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{
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memory_region_init_ram(mr, NULL, name, size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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/* Create an alias of an entire original MemoryRegion @orig
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* located at @base in the memory map.
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*/
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static void make_ram_alias(MemoryRegion *mr, const char *name,
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MemoryRegion *orig, hwaddr base)
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{
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memory_region_init_alias(mr, NULL, name, orig, 0,
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memory_region_size(orig));
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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static void mps2_common_init(MachineState *machine)
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{
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MPS2MachineState *mms = MPS2_MACHINE(machine);
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MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
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MemoryRegion *system_memory = get_system_memory();
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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DeviceState *armv7m, *sccdev;
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if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
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error_report("This board can only be used with CPU %s",
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mc->default_cpu_type);
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exit(1);
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}
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/* The FPGA images have an odd combination of different RAMs,
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* because in hardware they are different implementations and
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* connected to different buses, giving varying performance/size
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* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
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* call the 16MB our "system memory", as it's the largest lump.
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*
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* Common to both boards:
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* 0x21000000..0x21ffffff : PSRAM (16MB)
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* AN385 only:
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* 0x00000000 .. 0x003fffff : ZBT SSRAM1
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* 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
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* 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
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* 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
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* 0x01000000 .. 0x01003fff : block RAM (16K)
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* 0x01004000 .. 0x01007fff : mirror of above
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* 0x01008000 .. 0x0100bfff : mirror of above
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* 0x0100c000 .. 0x0100ffff : mirror of above
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* AN511 only:
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* 0x00000000 .. 0x0003ffff : FPGA block RAM
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* 0x00400000 .. 0x007fffff : ZBT SSRAM1
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* 0x20000000 .. 0x2001ffff : SRAM
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* 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
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*
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* The AN385 has a feature where the lowest 16K can be mapped
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* either to the bottom of the ZBT SSRAM1 or to the block RAM.
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* This is of no use for QEMU so we don't implement it (as if
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* zbt_boot_ctrl is always zero).
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*/
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memory_region_allocate_system_memory(&mms->psram,
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NULL, "mps.ram", 0x1000000);
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memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
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switch (mmc->fpga_type) {
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case FPGA_AN385:
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make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
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make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
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make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
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make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
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&mms->ssram23, 0x20400000);
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make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
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make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
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&mms->blockram, 0x01004000);
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make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
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&mms->blockram, 0x01008000);
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make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
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&mms->blockram, 0x0100c000);
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break;
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case FPGA_AN511:
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make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
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make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
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make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
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make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
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break;
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default:
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g_assert_not_reached();
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}
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object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M);
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armv7m = DEVICE(&mms->armv7m);
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qdev_set_parent_bus(armv7m, sysbus_get_default());
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switch (mmc->fpga_type) {
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case FPGA_AN385:
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qdev_prop_set_uint32(armv7m, "num-irq", 32);
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break;
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case FPGA_AN511:
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qdev_prop_set_uint32(armv7m, "num-irq", 64);
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break;
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default:
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g_assert_not_reached();
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}
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qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
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object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
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"memory", &error_abort);
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object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
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&error_fatal);
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create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
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create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
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create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
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create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
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create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
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create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
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/* These three ranges all cover multiple devices; we may implement
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* some of them below (in which case the real device takes precedence
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* over the unimplemented-region mapping).
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*/
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create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
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0x40000000, 0x00010000);
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create_unimplemented_device("CMSDK peripheral region @0x40010000",
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0x40010000, 0x00010000);
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create_unimplemented_device("Extra peripheral region @0x40020000",
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0x40020000, 0x00010000);
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create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
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create_unimplemented_device("VGA", 0x41000000, 0x0200000);
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switch (mmc->fpga_type) {
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case FPGA_AN385:
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{
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/* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
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* Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
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*/
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Object *orgate;
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DeviceState *orgate_dev;
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int i;
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orgate = object_new(TYPE_OR_IRQ);
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object_property_set_int(orgate, 6, "num-lines", &error_fatal);
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object_property_set_bool(orgate, true, "realized", &error_fatal);
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orgate_dev = DEVICE(orgate);
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qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
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for (i = 0; i < 5; i++) {
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static const hwaddr uartbase[] = {0x40004000, 0x40005000,
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0x40006000, 0x40007000,
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0x40009000};
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Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
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/* RX irq number; TX irq is always one greater */
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static const int uartirq[] = {0, 2, 4, 18, 20};
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qemu_irq txovrint = NULL, rxovrint = NULL;
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if (i < 3) {
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txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
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rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
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}
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cmsdk_apb_uart_create(uartbase[i],
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qdev_get_gpio_in(armv7m, uartirq[i] + 1),
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qdev_get_gpio_in(armv7m, uartirq[i]),
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txovrint, rxovrint,
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NULL,
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uartchr, SYSCLK_FRQ);
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}
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break;
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}
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case FPGA_AN511:
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{
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/* The overflow IRQs for all UARTs are ORed together.
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* Tx and Rx IRQs for each UART are ORed together.
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*/
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Object *orgate;
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DeviceState *orgate_dev;
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int i;
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orgate = object_new(TYPE_OR_IRQ);
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object_property_set_int(orgate, 10, "num-lines", &error_fatal);
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object_property_set_bool(orgate, true, "realized", &error_fatal);
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orgate_dev = DEVICE(orgate);
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qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
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for (i = 0; i < 5; i++) {
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/* system irq numbers for the combined tx/rx for each UART */
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static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
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static const hwaddr uartbase[] = {0x40004000, 0x40005000,
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0x4002c000, 0x4002d000,
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0x4002e000};
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Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
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Object *txrx_orgate;
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DeviceState *txrx_orgate_dev;
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txrx_orgate = object_new(TYPE_OR_IRQ);
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object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
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object_property_set_bool(txrx_orgate, true, "realized",
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&error_fatal);
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txrx_orgate_dev = DEVICE(txrx_orgate);
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qdev_connect_gpio_out(txrx_orgate_dev, 0,
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qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
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cmsdk_apb_uart_create(uartbase[i],
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qdev_get_gpio_in(txrx_orgate_dev, 0),
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qdev_get_gpio_in(txrx_orgate_dev, 1),
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qdev_get_gpio_in(orgate_dev, i * 2),
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qdev_get_gpio_in(orgate_dev, i * 2 + 1),
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NULL,
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uartchr, SYSCLK_FRQ);
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}
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break;
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}
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default:
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g_assert_not_reached();
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}
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cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
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cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
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object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
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sccdev = DEVICE(&mms->scc);
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qdev_set_parent_bus(sccdev, sysbus_get_default());
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qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
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qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
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qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
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object_property_set_bool(OBJECT(&mms->scc), true, "realized",
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&error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
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/* In hardware this is a LAN9220; the LAN9118 is software compatible
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* except that it doesn't support the checksum-offload feature.
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*/
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lan9118_init(&nd_table[0], 0x40200000,
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qdev_get_gpio_in(armv7m,
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mmc->fpga_type == FPGA_AN385 ? 13 : 47));
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system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
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armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
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0x400000);
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}
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static void mps2_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->init = mps2_common_init;
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mc->max_cpus = 1;
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}
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static void mps2_an385_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
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mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
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mmc->fpga_type = FPGA_AN385;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
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mmc->scc_id = 0x41040000 | (385 << 4);
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}
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static void mps2_an511_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
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mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
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mmc->fpga_type = FPGA_AN511;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
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mmc->scc_id = 0x4104000 | (511 << 4);
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}
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static const TypeInfo mps2_info = {
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.name = TYPE_MPS2_MACHINE,
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.parent = TYPE_MACHINE,
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.abstract = true,
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.instance_size = sizeof(MPS2MachineState),
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.class_size = sizeof(MPS2MachineClass),
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.class_init = mps2_class_init,
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};
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static const TypeInfo mps2_an385_info = {
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.name = TYPE_MPS2_AN385_MACHINE,
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.parent = TYPE_MPS2_MACHINE,
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.class_init = mps2_an385_class_init,
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};
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static const TypeInfo mps2_an511_info = {
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.name = TYPE_MPS2_AN511_MACHINE,
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.parent = TYPE_MPS2_MACHINE,
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.class_init = mps2_an511_class_init,
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};
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static void mps2_machine_init(void)
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{
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type_register_static(&mps2_info);
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type_register_static(&mps2_an385_info);
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type_register_static(&mps2_an511_info);
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}
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type_init(mps2_machine_init);
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